Floating-point down convert to BFloat16 format (predicated).
Convert to BFloat16 from single-precision in each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified.
Since the result type is smaller than the input type, the results are zero-extended to fill each destination element.
Unlike the BFloat16 matrix multiplication and dot product instructions, this instruction honors all of the FPCR bits that apply to single-precision arithmetic. It can also generate a floating-point exception that causes cumulative exception bits in the FPSR to be set, or a synchronous exception to be taken, depending on the enable bits in the FPCR.
ID_AA64ZFR0_EL1.BF16 indicates whether this instruction is implemented.
if !HaveSVE() || !HaveBF16Ext() then UNDEFINED; integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Zd);
Is the name of the destination scalable vector register, encoded in the "Zd" field.
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
Is the name of the source scalable vector register, encoded in the "Zn" field.
CheckSVEEnabled(); integer elements = VL DIV 32; bits(PL) mask = P[g]; bits(VL) operand = Z[n]; bits(VL) result = Z[d]; for e = 0 to elements-1 bits(32) element = Elem[operand, e, 32]; if ElemP[mask, e, 32] == '1' then Elem[result, 2*e, 16] = FPConvertBF(element, FPCR); Elem[result, 2*e+1, 16] = Zeros(); Z[d] = result;
This instruction might be immediately preceded in program order by a MOVPRFX instruction that conforms to all of the following requirements, otherwise the behavior of either or both instructions is unpredictable:
- The MOVPRFX instruction must specify the same destination register as this instruction.
- The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.
- An unpredicated MOVPRFX instruction.
- A predicated MOVPRFX instruction using the same governing predicate register and source element size as this instruction.