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Top-level encodings for A64

313029282726252423222120191817161514131211109876543210
op0

Reserved

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op00000op1
Decode fields Instruction details
op0op1
000 000000000 UDF
!= 000000000 UNALLOCATED
!= 000 UNALLOCATED

SVE encodings

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op00010op1op2op3
Decode fields Instruction details
op0op1op2op3
000 0x 0xxxx x1xxxx SVE Integer Multiply-Add - Predicated
000 0x 0xxxx 000xxx SVE Integer Binary Arithmetic - Predicated
000 0x 0xxxx 001xxx SVE Integer Reduction
000 0x 0xxxx 100xxx SVE Bitwise Shift - Predicated
000 0x 0xxxx 101xxx SVE Integer Unary Arithmetic - Predicated
000 0x 1xxxx 000xxx SVE integer add/subtract vectors (unpredicated)
000 0x 1xxxx 001xxx SVE Bitwise Logical - Unpredicated
000 0x 1xxxx 0100xx SVE Index Generation
000 0x 1xxxx 0101xx SVE Stack Allocation
000 0x 1xxxx 011xxx UNALLOCATED
000 0x 1xxxx 100xxx SVE Bitwise Shift - Unpredicated
000 0x 1xxxx 1010xx SVE address generation
000 0x 1xxxx 1011xx SVE Integer Misc - Unpredicated
000 0x 1xxxx 11xxxx SVE Element Count
000 1x 00xxx SVE Bitwise Immediate
000 1x 01xxx SVE Integer Wide Immediate - Predicated
000 1x 1xxxx 001xxx SVE Permute Vector - Unpredicated
000 1x 1xxxx 010xxx SVE Permute Predicate
000 1x 1xxxx 011xxx SVE permute vector elements
000 1x 1xxxx 10xxxx SVE Permute Vector - Predicated
000 1x 1xxxx 11xxxx SEL (vectors)
000 10 1xxxx 000xxx SVE Permute Vector - Extract
000 11 1xxxx 000xxx SVE permute vector segments
001 0x 0xxxx SVE Integer Compare - Vectors
001 0x 1xxxx SVE integer compare with unsigned immediate
001 1x 0xxxx x0xxxx SVE integer compare with signed immediate
001 1x 00xxx 01xxxx SVE predicate logical operations
001 1x 00xxx 11xxxx SVE Propagate Break
001 1x 01xxx 01xxxx SVE Partition Break
001 1x 01xxx 11xxxx SVE Predicate Misc
001 1x 1xxxx 00xxxx SVE Integer Compare - Scalars
001 1x 1xxxx 01xxxx UNALLOCATED
001 1x 1xxxx 11xxxx SVE Integer Wide Immediate - Unpredicated
001 1x 100xx 10xxxx SVE predicate count
001 1x 101xx 1000xx SVE Inc/Dec by Predicate Count
001 1x 101xx 1001xx SVE Write FFR
001 1x 101xx 101xxx UNALLOCATED
001 1x 11xxx 10xxxx UNALLOCATED
010 0x 0xxxx 0xxxxx SVE Integer Multiply-Add - Unpredicated
010 0x 0xxxx 1xxxxx UNALLOCATED
010 0x 1xxxx SVE Multiply - Indexed
010 1x 0xxxx 0xxxxx UNALLOCATED
010 1x 0xxxx 10xxxx SVE Misc
010 1x 0xxxx 11xxxx UNALLOCATED
010 1x 1xxxx UNALLOCATED
011 0x 0xxxx 0xxxxx FCMLA (vectors)
011 0x 00x1x 1xxxxx UNALLOCATED
011 0x 00000 100xxx FCADD
011 0x 00000 101xxx UNALLOCATED
011 0x 00000 11xxxx UNALLOCATED
011 0x 00001 1xxxxx UNALLOCATED
011 0x 0010x 100xxx UNALLOCATED
011 0x 0010x 101xxx SVE floating-point convert precision odd elements
011 0x 0010x 11xxxx UNALLOCATED
011 0x 01xxx 1xxxxx UNALLOCATED
011 0x 1xxxx x0x01x UNALLOCATED
011 0x 1xxxx 00000x SVE floating-point multiply-add (indexed)
011 0x 1xxxx 0001xx SVE floating-point complex multiply-add (indexed)
011 0x 1xxxx 001000 SVE floating-point multiply (indexed)
011 0x 1xxxx 001001 UNALLOCATED
011 0x 1xxxx 0011xx UNALLOCATED
011 0x 1xxxx 01x0xx SVE Floating Point Widening Multiply-Add - Indexed
011 0x 1xxxx 01x1xx UNALLOCATED
011 0x 1xxxx 10x00x SVE Floating Point Widening Multiply-Add
011 0x 1xxxx 10x1xx UNALLOCATED
011 0x 1xxxx 110xxx UNALLOCATED
011 0x 1xxxx 111000 UNALLOCATED
011 0x 1xxxx 111001 SVE floating point matrix multiply accumulate
011 0x 1xxxx 11101x UNALLOCATED
011 0x 1xxxx 1111xx UNALLOCATED
011 1x 0xxxx x1xxxx SVE floating-point compare vectors
011 1x 0xxxx 000xxx SVE floating-point arithmetic (unpredicated)
011 1x 0xxxx 100xxx SVE Floating Point Arithmetic - Predicated
011 1x 0xxxx 101xxx SVE Floating Point Unary Operations - Predicated
011 1x 000xx 001xxx SVE floating-point recursive reduction
011 1x 001xx 0010xx UNALLOCATED
011 1x 001xx 0011xx SVE Floating Point Unary Operations - Unpredicated
011 1x 010xx 001xxx SVE Floating Point Compare - with Zero
011 1x 011xx 001xxx SVE floating-point serial reduction (predicated)
011 1x 1xxxx SVE Floating Point Multiply-Add
100 SVE Memory - 32-bit Gather and Unsized Contiguous
101 SVE Memory - Contiguous Load
110 SVE Memory - 64-bit Gather
111 0x0xxx SVE Memory - Contiguous Store and Unsized Contiguous
111 0x1xxx SVE Memory - Non-temporal and Multi-register Store
111 1x0xxx SVE Memory - Scatter with Optional Sign Extend
111 101xxx SVE Memory - Scatter
111 111xxx SVE Memory - Contiguous Store with Immediate Offset

SVE Integer Multiply-Add - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001000op01

SVE integer multiply-accumulate writing addend (predicated)

These instructions are under SVE Integer Multiply-Add - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size0Zm01opPgZnZda
Decode fields Instruction Details
op
0 MLA
1 MLS

SVE integer multiply-add writing multiplicand (predicated)

These instructions are under SVE Integer Multiply-Add - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size0Zm11opPgZaZdn
Decode fields Instruction Details
op
0 MAD
1 MSB

SVE Integer Binary Arithmetic - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001000op0000

SVE integer add/subtract vectors (predicated)

These instructions are under SVE Integer Binary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size000opc000PgZmZdn
Decode fields Instruction Details
opc
000 ADD (vectors, predicated)
001 SUB (vectors, predicated)
010 UNALLOCATED
011 SUBR (vectors)
1xx UNALLOCATED

SVE integer min/max/difference (predicated)

These instructions are under SVE Integer Binary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size001opcU000PgZmZdn
Decode fields Instruction Details
opc U
00 0 SMAX (vectors)
00 1 UMAX (vectors)
01 0 SMIN (vectors)
01 1 UMIN (vectors)
10 0 SABD
10 1 UABD
11 UNALLOCATED

SVE integer multiply vectors (predicated)

These instructions are under SVE Integer Binary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size0100HU000PgZmZdn
Decode fields Instruction Details
H U
0 0 MUL (vectors)
0 1 UNALLOCATED
1 0 SMULH
1 1 UMULH

SVE integer divide vectors (predicated)

These instructions are under SVE Integer Binary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size0101RU000PgZmZdn
Decode fields Instruction Details
R U
0 0 SDIV
0 1 UDIV
1 0 SDIVR
1 1 UDIVR

SVE bitwise logical operations (predicated)

These instructions are under SVE Integer Binary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size011opc000PgZmZdn
Decode fields Instruction Details
opc
000 ORR (vectors, predicated)
001 EOR (vectors, predicated)
010 AND (vectors, predicated)
011 BIC (vectors, predicated)
1xx UNALLOCATED

SVE Integer Reduction

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001000op0001

SVE integer add reduction (predicated)

These instructions are under SVE Integer Reduction.

313029282726252423222120191817161514131211109876543210
00000100size000opcU001PgZnVd
Decode fields Instruction Details
opc U
00 0 SADDV
00 1 UADDV
01 UNALLOCATED
1x UNALLOCATED

SVE integer min/max reduction (predicated)

These instructions are under SVE Integer Reduction.

313029282726252423222120191817161514131211109876543210
00000100size001opcU001PgZnVd
Decode fields Instruction Details
opc U
00 0 SMAXV
00 1 UMAXV
01 0 SMINV
01 1 UMINV
1x UNALLOCATED

SVE constructive prefix (predicated)

These instructions are under SVE Integer Reduction.

313029282726252423222120191817161514131211109876543210
00000100size010opcM001PgZnZd
Decode fields Instruction Details
opc
00 MOVPRFX (predicated)
01 UNALLOCATED
1x UNALLOCATED

SVE bitwise logical reduction (predicated)

These instructions are under SVE Integer Reduction.

313029282726252423222120191817161514131211109876543210
00000100size011opc001PgZnVd
Decode fields Instruction Details
opc
000 ORV
001 EORV
010 ANDV
011 UNALLOCATED
1xx UNALLOCATED

SVE Bitwise Shift - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001000op0100

SVE bitwise shift by immediate (predicated)

These instructions are under SVE Bitwise Shift - Predicated.

313029282726252423222120191817161514131211109876543210
00000100tszh00opcLU100Pgtszlimm3Zdn
Decode fields Instruction Details
opc L U
00 0 0 ASR (immediate, predicated)
00 0 1 LSR (immediate, predicated)
00 1 0 UNALLOCATED
00 1 1 LSL (immediate, predicated)
01 0 0 ASRD
01 0 1 UNALLOCATED
01 1 UNALLOCATED
1x UNALLOCATED

SVE bitwise shift by vector (predicated)

These instructions are under SVE Bitwise Shift - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size010RLU100PgZmZdn
Decode fields Instruction Details
R L U
1 0 UNALLOCATED
0 0 0 ASR (vectors)
0 0 1 LSR (vectors)
0 1 1 LSL (vectors)
1 0 0 ASRR
1 0 1 LSRR
1 1 1 LSLR

SVE bitwise shift by wide elements (predicated)

These instructions are under SVE Bitwise Shift - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size011RLU100PgZmZdn
Decode fields Instruction Details
R L U
0 0 0 ASR (wide elements, predicated)
0 0 1 LSR (wide elements, predicated)
0 1 0 UNALLOCATED
0 1 1 LSL (wide elements, predicated)
1 UNALLOCATED

SVE Integer Unary Arithmetic - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001000op0101
Decode fields Instruction details
op0
0x UNALLOCATED
10 SVE integer unary operations (predicated)
11 SVE bitwise unary operations (predicated)

SVE integer unary operations (predicated)

These instructions are under SVE Integer Unary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size010opc101PgZnZd
Decode fields Instruction Details
opc
000 SXTB, SXTH, SXTWSXTB
001 UXTB, UXTH, UXTWUXTB
010 SXTB, SXTH, SXTWSXTH
011 UXTB, UXTH, UXTWUXTH
100 SXTB, SXTH, SXTWSXTW
101 UXTB, UXTH, UXTWUXTW
110 ABS
111 NEG

SVE bitwise unary operations (predicated)

These instructions are under SVE Integer Unary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size011opc101PgZnZd
Decode fields Instruction Details
opc
000 CLS
001 CLZ
010 CNT
011 CNOT
100 FABS
101 FNEG
110 NOT (vector)
111 UNALLOCATED

SVE integer add/subtract vectors (unpredicated)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00000100size1Zm000opcZnZd
Decode fields Instruction Details
opc
000 ADD (vectors, unpredicated)
001 SUB (vectors, unpredicated)
01x UNALLOCATED
100 SQADD (vectors)
101 UQADD (vectors)
110 SQSUB (vectors)
111 UQSUB (vectors)

SVE Bitwise Logical - Unpredicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001001001op0op1
Decode fields Instruction details
op0op1
0 UNALLOCATED
1 00 SVE bitwise logical operations (unpredicated)
1 != 00 UNALLOCATED

SVE bitwise logical operations (unpredicated)

These instructions are under SVE Bitwise Logical - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100opc1Zm001100ZnZd

SVE Index Generation

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
0000010010100op0

SVE Stack Allocation

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00000100op010101op1
Decode fields Instruction details
op0op1
0 0 SVE stack frame adjustment
1 0 SVE stack frame size
1 UNALLOCATED

SVE stack frame adjustment

These instructions are under SVE Stack Allocation.

313029282726252423222120191817161514131211109876543210
000001000op1Rn01010imm6Rd
Decode fields Instruction Details
op
0 ADDVL
1 ADDPL

SVE stack frame size

These instructions are under SVE Stack Allocation.

313029282726252423222120191817161514131211109876543210
000001001op1opc201010imm6Rd
Decode fields Instruction Details
op opc2
0 0xxxx UNALLOCATED
0 10xxx UNALLOCATED
0 110xx UNALLOCATED
0 1110x UNALLOCATED
0 11110 UNALLOCATED
0 11111 RDVL
1 UNALLOCATED

SVE Bitwise Shift - Unpredicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001001100op0

SVE bitwise shift by wide elements (unpredicated)

These instructions are under SVE Bitwise Shift - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100size1Zm1000opcZnZd
Decode fields Instruction Details
opc
00 ASR (wide elements, unpredicated)
01 LSR (wide elements, unpredicated)
10 UNALLOCATED
11 LSL (wide elements, unpredicated)

SVE bitwise shift by immediate (unpredicated)

These instructions are under SVE Bitwise Shift - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100tszh1tszlimm31001opcZnZd
Decode fields Instruction Details
opc
00 ASR (immediate, unpredicated)
01 LSR (immediate, unpredicated)
10 UNALLOCATED
11 LSL (immediate, unpredicated)

SVE address generation

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00000100opc1Zm1010mszZnZd
Decode fields Instruction Details
opc
00 ADRUnpacked 32-bit signed offsets
01 ADRUnpacked 32-bit unsigned offsets
1x ADRPacked offsets

SVE Integer Misc - Unpredicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
0000010011011op0

SVE floating-point trig select coefficient

These instructions are under SVE Integer Misc - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100size1Zm10110opZnZd
Decode fields Instruction Details
op
0 FTSSEL
1 UNALLOCATED

SVE floating-point exponential accelerator

These instructions are under SVE Integer Misc - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100size1opc101110ZnZd
Decode fields Instruction Details
opc
00000 FEXPA
00001 UNALLOCATED
0001x UNALLOCATED
001xx UNALLOCATED
01xxx UNALLOCATED
1xxxx UNALLOCATED

SVE constructive prefix (unpredicated)

These instructions are under SVE Integer Misc - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100opc1opc2101111ZnZd
Decode fields Instruction Details
opc opc2
00 00000 MOVPRFX (unpredicated)
00 00001 UNALLOCATED
00 0001x UNALLOCATED
00 001xx UNALLOCATED
00 01xxx UNALLOCATED
00 1xxxx UNALLOCATED
01 UNALLOCATED
1x UNALLOCATED

SVE Element Count

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001001op011op1
Decode fields Instruction details
op0op1
0 00x SVE saturating inc/dec vector by element count
0 100 SVE element count
0 101 UNALLOCATED
1 000 SVE inc/dec vector by element count
1 100 SVE inc/dec register by element count
1 x01 UNALLOCATED
01x UNALLOCATED
11x SVE saturating inc/dec register by element count

SVE saturating inc/dec vector by element count

These instructions are under SVE Element Count.

313029282726252423222120191817161514131211109876543210
00000100size10imm41100DUpatternZdn
Decode fields Instruction Details
size D U
00 UNALLOCATED
01 0 0 SQINCH (vector)
01 0 1 UQINCH (vector)
01 1 0 SQDECH (vector)
01 1 1 UQDECH (vector)
10 0 0 SQINCW (vector)
10 0 1 UQINCW (vector)
10 1 0 SQDECW (vector)
10 1 1 UQDECW (vector)
11 0 0 SQINCD (vector)
11 0 1 UQINCD (vector)
11 1 0 SQDECD (vector)
11 1 1 UQDECD (vector)

SVE element count

These instructions are under SVE Element Count.

313029282726252423222120191817161514131211109876543210
00000100size10imm411100oppatternRd
Decode fields Instruction Details
size op
1 UNALLOCATED
00 0 CNTB, CNTD, CNTH, CNTWCNTB
01 0 CNTB, CNTD, CNTH, CNTWCNTH
10 0 CNTB, CNTD, CNTH, CNTWCNTW
11 0 CNTB, CNTD, CNTH, CNTWCNTD

SVE inc/dec vector by element count

These instructions are under SVE Element Count.

313029282726252423222120191817161514131211109876543210
00000100size11imm411000DpatternZdn
Decode fields Instruction Details
size D
00 UNALLOCATED
01 0 INCD, INCH, INCW (vector)INCH
01 1 DECD, DECH, DECW (vector)DECH
10 0 INCD, INCH, INCW (vector)INCW
10 1 DECD, DECH, DECW (vector)DECW
11 0 INCD, INCH, INCW (vector)INCD
11 1 DECD, DECH, DECW (vector)DECD

SVE inc/dec register by element count

These instructions are under SVE Element Count.

313029282726252423222120191817161514131211109876543210
00000100size11imm411100DpatternRdn

SVE saturating inc/dec register by element count

These instructions are under SVE Element Count.

313029282726252423222120191817161514131211109876543210
00000100size1sfimm41111DUpatternRdn
Decode fields Instruction Details
size sf D U
00 0 0 0 SQINCB32-bit
00 0 0 1 UQINCB32-bit
00 0 1 0 SQDECB32-bit
00 0 1 1 UQDECB32-bit
00 1 0 0 SQINCB64-bit
00 1 0 1 UQINCB64-bit
00 1 1 0 SQDECB64-bit
00 1 1 1 UQDECB64-bit
01 0 0 0 SQINCH (scalar)32-bit
01 0 0 1 UQINCH (scalar)32-bit
01 0 1 0 SQDECH (scalar)32-bit
01 0 1 1 UQDECH (scalar)32-bit
01 1 0 0 SQINCH (scalar)64-bit
01 1 0 1 UQINCH (scalar)64-bit
01 1 1 0 SQDECH (scalar)64-bit
01 1 1 1 UQDECH (scalar)64-bit
10 0 0 0 SQINCW (scalar)32-bit
10 0 0 1 UQINCW (scalar)32-bit
10 0 1 0 SQDECW (scalar)32-bit
10 0 1 1 UQDECW (scalar)32-bit
10 1 0 0 SQINCW (scalar)64-bit
10 1 0 1 UQINCW (scalar)64-bit
10 1 1 0 SQDECW (scalar)64-bit
10 1 1 1 UQDECW (scalar)64-bit
11 0 0 0 SQINCD (scalar)32-bit
11 0 0 1 UQINCD (scalar)32-bit
11 0 1 0 SQDECD (scalar)32-bit
11 0 1 1 UQDECD (scalar)32-bit
11 1 0 0 SQINCD (scalar)64-bit
11 1 0 1 UQINCD (scalar)64-bit
11 1 1 0 SQDECD (scalar)64-bit
11 1 1 1 UQDECD (scalar)64-bit

SVE Bitwise Immediate

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00000101op000op1
Decode fields Instruction details
op0op1
11 00 DUPM
!= 11 00 SVE bitwise logical with immediate (unpredicated)
!= 00 UNALLOCATED

SVE bitwise logical with immediate (unpredicated)

These instructions are under SVE Bitwise Immediate.

313029282726252423222120191817161514131211109876543210
00000101!= 110000imm13Zdn
opc

The following constraints also apply to this encoding: opc != 11 && opc != 11

Decode fields Instruction Details
opc
00 ORR (immediate)
01 EOR (immediate)
10 AND (immediate)

SVE Integer Wide Immediate - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
0000010101op0
Decode fields Instruction details
op0
0xx SVE copy integer immediate (predicated)
10x UNALLOCATED
110 FCPY
111 UNALLOCATED

SVE copy integer immediate (predicated)

These instructions are under SVE Integer Wide Immediate - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size01Pg0Mshimm8Zd
Decode fields Instruction Details
M
0 CPY (immediate, zeroing)
1 CPY (immediate, merging)

SVE Permute Vector - Unpredicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001011op0op1op2001op3op4
Decode fields Instruction details
op0op1op2op3op4
00 00 0 1 10 DUP (scalar)
00 10 0 1 10 INSR (scalar)
00 x0 0 0 01 UNALLOCATED
00 x0 0 1 x1 UNALLOCATED
00 x1 1 1x UNALLOCATED
00 x1 01 UNALLOCATED
00 1 1 1x UNALLOCATED
00 1 01 UNALLOCATED
00 0 1x UNALLOCATED
01 != 00 UNALLOCATED
10 0x 0 01 UNALLOCATED
10 0x 1 10 SVE unpack vector elements
10 0x 1 x1 UNALLOCATED
10 10 0 0 01 UNALLOCATED
10 10 0 1 10 INSR (SIMD&FP scalar)
10 10 0 1 x1 UNALLOCATED
10 11 1 1x UNALLOCATED
10 11 01 UNALLOCATED
10 1x 1 1 1x UNALLOCATED
10 1x 1 01 UNALLOCATED
11 00 0 0 01 UNALLOCATED
11 00 0 1 10 REV (vector)
11 00 0 1 x1 UNALLOCATED
11 0x 1 1 1x UNALLOCATED
11 0x 1 01 UNALLOCATED
11 != 00 1 1x UNALLOCATED
11 != 00 01 UNALLOCATED
1x 0 1x UNALLOCATED
0 00 DUP (indexed)
1 00 TBL

SVE unpack vector elements

These instructions are under SVE Permute Vector - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000101size1100UH001110ZnZd
Decode fields Instruction Details
U H
0 0 SUNPKHI, SUNPKLOSUNPKLO
0 1 SUNPKHI, SUNPKLOSUNPKHI
1 0 UUNPKHI, UUNPKLOUUNPKLO
1 1 UUNPKHI, UUNPKLOUUNPKHI

SVE Permute Predicate

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00000101op01op1010op2op3
Decode fields Instruction details
op0op1op2op3
00 1000x 0000 0 SVE unpack predicate elements
01 1000x 0000 0 UNALLOCATED
10 1000x 0000 0 UNALLOCATED
11 1000x 0000 0 UNALLOCATED
0xxxx xxx0 0 SVE permute predicate elements
0xxxx xxx1 0 UNALLOCATED
10100 0000 0 REV (predicate)
10101 0000 0 UNALLOCATED
10x0x 1000 0 UNALLOCATED
10x0x x100 0 UNALLOCATED
10x0x xx10 0 UNALLOCATED
10x0x xxx1 0 UNALLOCATED
10x1x 0 UNALLOCATED
11xxx 0 UNALLOCATED
1 UNALLOCATED

SVE unpack predicate elements

These instructions are under SVE Permute Predicate.

313029282726252423222120191817161514131211109876543210
000001010011000H0100000Pn0Pd
Decode fields Instruction Details
H
0 PUNPKHI, PUNPKLOPUNPKLO
1 PUNPKHI, PUNPKLOPUNPKHI

SVE permute predicate elements

These instructions are under SVE Permute Predicate.

313029282726252423222120191817161514131211109876543210
00000101size10Pm010opcH0Pn0Pd
Decode fields Instruction Details
opc H
00 0 ZIP1, ZIP2 (predicates)ZIP1
00 1 ZIP1, ZIP2 (predicates)ZIP2
01 0 UZP1, UZP2 (predicates)UZP1
01 1 UZP1, UZP2 (predicates)UZP2
10 0 TRN1, TRN2 (predicates)TRN1
10 1 TRN1, TRN2 (predicates)TRN2
11 UNALLOCATED

SVE permute vector elements

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00000101size1Zm011opcZnZd
Decode fields Instruction Details
opc
000 ZIP1, ZIP2 (vectors)ZIP1
001 ZIP1, ZIP2 (vectors)ZIP2
010 UZP1, UZP2 (vectors)UZP1
011 UZP1, UZP2 (vectors)UZP2
100 TRN1, TRN2 (vectors)TRN1
101 TRN1, TRN2 (vectors)TRN2
11x UNALLOCATED

SVE Permute Vector - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00000101op01op1op2op310op4
Decode fields Instruction details
op0op1op2op3op4
0 0 000 1 0 UNALLOCATED
1 0 000 1 0 COMPACT
0 000 0 0 CPY (SIMD&FP scalar)
0 000 1 SVE extract element to general register
0 001 0 SVE extract element to SIMD&FP scalar register
0 01x 0 SVE reverse within elements
0 01x 1 UNALLOCATED
0 100 0 1 CPY (scalar)
0 100 1 1 UNALLOCATED
0 100 0 SVE conditionally broadcast element to vector
0 101 0 SVE conditionally extract element to SIMD&FP scalar
0 110 0 0 SPLICE
0 110 0 1 UNALLOCATED
0 110 1 UNALLOCATED
0 111 0 UNALLOCATED
0 111 1 UNALLOCATED
0 x01 1 UNALLOCATED
1 000 0 UNALLOCATED
1 000 1 SVE conditionally extract element to general register
1 != 000 UNALLOCATED

SVE extract element to general register

These instructions are under SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size10000B101PgZnRd
Decode fields Instruction Details
B
0 LASTA (scalar)
1 LASTB (scalar)

SVE extract element to SIMD&FP scalar register

These instructions are under SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size10001B100PgZnVd
Decode fields Instruction Details
B
0 LASTA (SIMD&FP scalar)
1 LASTB (SIMD&FP scalar)

SVE reverse within elements

These instructions are under SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size1001opc100PgZnZd
Decode fields Instruction Details
opc
00 REVB, REVH, REVWREVB
01 REVB, REVH, REVWREVH
10 REVB, REVH, REVWREVW
11 RBIT

SVE conditionally broadcast element to vector

These instructions are under SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size10100B100PgZmZdn
Decode fields Instruction Details
B
0 CLASTA (vectors)
1 CLASTB (vectors)

SVE conditionally extract element to SIMD&FP scalar

These instructions are under SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size10101B100PgZmVdn
Decode fields Instruction Details
B
0 CLASTA (SIMD&FP scalar)
1 CLASTB (SIMD&FP scalar)

SVE conditionally extract element to general register

These instructions are under SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size11000B101PgZmRdn
Decode fields Instruction Details
B
0 CLASTA (scalar)
1 CLASTB (scalar)

SVE Permute Vector - Extract

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001010op01000
Decode fields Instruction details
op0
0 EXT
1 UNALLOCATED

SVE permute vector segments

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001011op1Zm000opc2ZnZd
Decode fields Instruction Details
op opc2
0 000 ZIP1, ZIP2 (vectors)ZIP1
0 001 ZIP1, ZIP2 (vectors)ZIP2
0 010 UZP1, UZP2 (vectors)UZP1
0 011 UZP1, UZP2 (vectors)UZP2
0 10x UNALLOCATED
0 110 TRN1, TRN2 (vectors)TRN1
0 111 TRN1, TRN2 (vectors)TRN2
1 UNALLOCATED

SVE Integer Compare - Vectors

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
001001000op0

SVE integer compare vectors

These instructions are under SVE Integer Compare - Vectors.

313029282726252423222120191817161514131211109876543210
00100100size0Zmop0o2PgZnnePd
Decode fields Instruction Details
op o2 ne
0 0 0 CMP<cc> (vectors)CMPHS
0 0 1 CMP<cc> (vectors)CMPHI
0 1 0 CMP<cc> (wide elements)CMPEQ
0 1 1 CMP<cc> (wide elements)CMPNE
1 0 0 CMP<cc> (vectors)CMPGE
1 0 1 CMP<cc> (vectors)CMPGT
1 1 0 CMP<cc> (vectors)CMPEQ
1 1 1 CMP<cc> (vectors)CMPNE

SVE integer compare with wide elements

These instructions are under SVE Integer Compare - Vectors.

313029282726252423222120191817161514131211109876543210
00100100size0ZmU1ltPgZnnePd

SVE integer compare with unsigned immediate

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00100100size1imm7ltPgZnnePd
Decode fields Instruction Details
lt ne
0 0 CMP<cc> (immediate)CMPHS
0 1 CMP<cc> (immediate)CMPHI
1 0 CMP<cc> (immediate)CMPLO
1 1 CMP<cc> (immediate)CMPLS

SVE integer compare with signed immediate

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101size0imm5op0o2PgZnnePd
Decode fields Instruction Details
op o2 ne
0 0 0 CMP<cc> (immediate)CMPGE
0 0 1 CMP<cc> (immediate)CMPGT
0 1 0 CMP<cc> (immediate)CMPLT
0 1 1 CMP<cc> (immediate)CMPLE
1 0 0 CMP<cc> (immediate)CMPEQ
1 0 1 CMP<cc> (immediate)CMPNE
1 1 UNALLOCATED


SVE Propagate Break

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
001001010011op0
Decode fields Instruction details
op0
0 SVE propagate break from previous partition
1 UNALLOCATED

SVE propagate break from previous partition

These instructions are under SVE Propagate Break.

313029282726252423222120191817161514131211109876543210
00100101opS00Pm11Pg0PnBPd

SVE Partition Break

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101op001op101op2op3
Decode fields Instruction details
op0op1op2op3
0 1000 0 0 SVE propagate break to next partition
0 1000 0 1 UNALLOCATED
0 x000 1 UNALLOCATED
0 x1xx UNALLOCATED
0 xx1x UNALLOCATED
0 xxx1 UNALLOCATED
1 0000 1 UNALLOCATED
1 != 0000 UNALLOCATED
0000 0 SVE partition break condition

SVE propagate break to next partition

These instructions are under SVE Partition Break.

313029282726252423222120191817161514131211109876543210
001001010S01100001Pg0Pn0Pdm

SVE partition break condition

These instructions are under SVE Partition Break.

313029282726252423222120191817161514131211109876543210
00100101BS01000001Pg0PnMPd

SVE Predicate Misc

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
0010010101op011op1op2op3op4
Decode fields Instruction details
op0op1op2op3op4
0000 x0 0 SVE predicate test
0100 x0 0 UNALLOCATED
0x10 x0 0 UNALLOCATED
0xx1 x0 0 UNALLOCATED
0xxx x1 0 UNALLOCATED
1000 000 00 0 SVE predicate first active
1000 000 != 00 0 UNALLOCATED
1000 100 10 0000 0 SVE predicate zero
1000 100 10 != 0000 0 UNALLOCATED
1000 110 00 0 SVE predicate read from FFR (predicated)
1001 000 0x 0 UNALLOCATED
1001 000 10 0 PNEXT
1001 000 11 0 UNALLOCATED
1001 100 10 0 UNALLOCATED
1001 110 00 0000 0 SVE predicate read from FFR (unpredicated)
1001 110 00 != 0000 0 UNALLOCATED
100x 010 0 UNALLOCATED
100x 100 0x 0 SVE predicate initialize
100x 100 11 0 UNALLOCATED
100x 110 != 00 0 UNALLOCATED
100x xx1 0 UNALLOCATED
110x 0 UNALLOCATED
1x1x 0 UNALLOCATED
1 UNALLOCATED

SVE predicate test

These instructions are under SVE Predicate Misc.

313029282726252423222120191817161514131211109876543210
00100101opS01000011Pg0Pn0opc2
Decode fields Instruction Details
op S opc2
0 0 UNALLOCATED
0 1 0000 PTEST
0 1 0001 UNALLOCATED
0 1 001x UNALLOCATED
0 1 01xx UNALLOCATED
0 1 1xxx UNALLOCATED
1 UNALLOCATED

SVE predicate first active

These instructions are under SVE Predicate Misc.

313029282726252423222120191817161514131211109876543210
00100101opS0110001100000Pg0Pdn
Decode fields Instruction Details
op S
0 0 UNALLOCATED
0 1 PFIRST
1 UNALLOCATED

SVE predicate zero

These instructions are under SVE Predicate Misc.

313029282726252423222120191817161514131211109876543210
00100101opS011000111001000000Pd
Decode fields Instruction Details
op S
0 0 PFALSE
0 1 UNALLOCATED
1 UNALLOCATED

SVE predicate read from FFR (predicated)

These instructions are under SVE Predicate Misc.

313029282726252423222120191817161514131211109876543210
00100101opS0110001111000Pg0Pd
Decode fields Instruction Details
op S
0 0 RDFFR, RDFFRS (predicated)not setting the condition flags
0 1 RDFFR, RDFFRS (predicated)setting the condition flags
1 UNALLOCATED

SVE predicate read from FFR (unpredicated)

These instructions are under SVE Predicate Misc.

313029282726252423222120191817161514131211109876543210
00100101opS011001111100000000Pd
Decode fields Instruction Details
op S
0 0 RDFFR (unpredicated)
0 1 UNALLOCATED
1 UNALLOCATED

SVE predicate initialize

These instructions are under SVE Predicate Misc.

313029282726252423222120191817161514131211109876543210
00100101size01100S111000pattern0Pd

SVE Integer Compare - Scalars

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101100op0op1op2
Decode fields Instruction details
op0op1op2
0 SVE integer compare scalar count and limit
1 000 0000 SVE conditionally terminate scalars
1 000 != 0000 UNALLOCATED
1 != 000 UNALLOCATED

SVE integer compare scalar count and limit

These instructions are under SVE Integer Compare - Scalars.

313029282726252423222120191817161514131211109876543210
00100101size1Rm000sfUltRneqPd
Decode fields Instruction Details
U lt eq
0 UNALLOCATED
0 1 0 WHILELT
0 1 1 WHILELE
1 1 0 WHILELO
1 1 1 WHILELS

SVE conditionally terminate scalars

These instructions are under SVE Integer Compare - Scalars.

313029282726252423222120191817161514131211109876543210
00100101opsz1Rm001000Rnne0000
Decode fields Instruction Details
op ne
0 UNALLOCATED
1 0 CTERMEQ, CTERMNECTERMEQ
1 1 CTERMEQ, CTERMNECTERMNE

SVE Integer Wide Immediate - Unpredicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
001001011op0op111

SVE integer add/subtract immediate (unpredicated)

These instructions are under SVE Integer Wide Immediate - Unpredicated.

313029282726252423222120191817161514131211109876543210
00100101size100opc11shimm8Zdn
Decode fields Instruction Details
opc
000 ADD (immediate)
001 SUB (immediate)
010 UNALLOCATED
011 SUBR (immediate)
100 SQADD (immediate)
101 UQADD (immediate)
110 SQSUB (immediate)
111 UQSUB (immediate)

SVE integer min/max immediate (unpredicated)

These instructions are under SVE Integer Wide Immediate - Unpredicated.

313029282726252423222120191817161514131211109876543210
00100101size101opc11o2imm8Zdn
Decode fields Instruction Details
opc o2
0xx 1 UNALLOCATED
000 0 SMAX (immediate)
001 0 UMAX (immediate)
010 0 SMIN (immediate)
011 0 UMIN (immediate)
1xx UNALLOCATED

SVE integer multiply immediate (unpredicated)

These instructions are under SVE Integer Wide Immediate - Unpredicated.

313029282726252423222120191817161514131211109876543210
00100101size110opc11o2imm8Zdn
Decode fields Instruction Details
opc o2
000 0 MUL (immediate)
000 1 UNALLOCATED
001 UNALLOCATED
01x UNALLOCATED
1xx UNALLOCATED

SVE broadcast integer immediate (unpredicated)

These instructions are under SVE Integer Wide Immediate - Unpredicated.

313029282726252423222120191817161514131211109876543210
00100101size111opc011shimm8Zd
Decode fields Instruction Details
opc
00 DUP (immediate)
01 UNALLOCATED
1x UNALLOCATED

SVE broadcast floating-point immediate (unpredicated)

These instructions are under SVE Integer Wide Immediate - Unpredicated.

313029282726252423222120191817161514131211109876543210
00100101size111opc111o2imm8Zd
Decode fields Instruction Details
opc o2
00 0 FDUP
00 1 UNALLOCATED
01 UNALLOCATED
1x UNALLOCATED

SVE predicate count

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101size100opc10Pgo2PnRd
Decode fields Instruction Details
opc o2
000 0 CNTP
000 1 UNALLOCATED
001 UNALLOCATED
01x UNALLOCATED
1xx UNALLOCATED

SVE Inc/Dec by Predicate Count

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101101op01000op1

SVE saturating inc/dec vector by predicate count

These instructions are under SVE Inc/Dec by Predicate Count.

313029282726252423222120191817161514131211109876543210
00100101size1010DU10000opcPmZdn
Decode fields Instruction Details
D U opc
01 UNALLOCATED
1x UNALLOCATED
0 0 00 SQINCP (vector)
0 1 00 UQINCP (vector)
1 0 00 SQDECP (vector)
1 1 00 UQDECP (vector)

SVE saturating inc/dec register by predicate count

These instructions are under SVE Inc/Dec by Predicate Count.

313029282726252423222120191817161514131211109876543210
00100101size1010DU10001sfopPmRdn
Decode fields Instruction Details
D U sf op
1 UNALLOCATED
0 0 0 0 SQINCP (scalar)32-bit
0 0 1 0 SQINCP (scalar)64-bit
0 1 0 0 UQINCP (scalar)32-bit
0 1 1 0 UQINCP (scalar)64-bit
1 0 0 0 SQDECP (scalar)32-bit
1 0 1 0 SQDECP (scalar)64-bit
1 1 0 0 UQDECP (scalar)32-bit
1 1 1 0 UQDECP (scalar)64-bit

SVE inc/dec vector by predicate count

These instructions are under SVE Inc/Dec by Predicate Count.

313029282726252423222120191817161514131211109876543210
00100101size1011opD10000opc2PmZdn
Decode fields Instruction Details
op D opc2
0 01 UNALLOCATED
0 1x UNALLOCATED
0 0 00 INCP (vector)
0 1 00 DECP (vector)
1 UNALLOCATED

SVE inc/dec register by predicate count

These instructions are under SVE Inc/Dec by Predicate Count.

313029282726252423222120191817161514131211109876543210
00100101size1011opD10001opc2PmRdn
Decode fields Instruction Details
op D opc2
0 01 UNALLOCATED
0 1x UNALLOCATED
0 0 00 INCP (scalar)
0 1 00 DECP (scalar)
1 UNALLOCATED

SVE Write FFR

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101101op0op11001op2op3op4
Decode fields Instruction details
op0op1op2op3op4
0 00 000 00000 SVE FFR write from predicate
1 00 000 0000 00000 SVE FFR initialise
1 00 000 1xxx 00000 UNALLOCATED
1 00 000 x1xx 00000 UNALLOCATED
1 00 000 xx1x 00000 UNALLOCATED
1 00 000 xxx1 00000 UNALLOCATED
00 000 != 00000 UNALLOCATED
00 != 000 UNALLOCATED
!= 00 UNALLOCATED

SVE FFR write from predicate

These instructions are under SVE Write FFR.

313029282726252423222120191817161514131211109876543210
00100101opc1010001001000Pn00000
Decode fields Instruction Details
opc
00 WRFFR
01 UNALLOCATED
1x UNALLOCATED

SVE FFR initialise

These instructions are under SVE Write FFR.

313029282726252423222120191817161514131211109876543210
00100101opc1011001001000000000000
Decode fields Instruction Details
opc
00 SETFFR
01 UNALLOCATED
1x UNALLOCATED

SVE Integer Multiply-Add - Unpredicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
0100010000op0op1op2
Decode fields Instruction details
op0op1op2
0 000 SVE integer dot product (unpredicated)
0 != 000 UNALLOCATED
1 0xx UNALLOCATED
1 10x UNALLOCATED
1 110 UNALLOCATED
1 111 0 SVE mixed sign dot product
1 111 1 UNALLOCATED

SVE integer dot product (unpredicated)

These instructions are under SVE Integer Multiply-Add - Unpredicated.

313029282726252423222120191817161514131211109876543210
01000100size0Zm00000UZnZda
Decode fields Instruction Details
U
0 SDOT (vectors)
1 UDOT (vectors)

SVE mixed sign dot product

These instructions are under SVE Integer Multiply-Add - Unpredicated.

313029282726252423222120191817161514131211109876543210
01000100size0Zm011110ZnZda
Decode fields Instruction Details
size
0x UNALLOCATED
10 USDOT (vectors)
11 UNALLOCATED

SVE Multiply - Indexed

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
010001001op0op1
Decode fields Instruction details
op0op1
000 00 SVE integer dot product (indexed)
000 01 UNALLOCATED
000 10 UNALLOCATED
000 11 SVE mixed sign dot product (indexed)
!= 000 UNALLOCATED

SVE integer dot product (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc00000UZnZda
Decode fields Instruction Details
size U
0x UNALLOCATED
10 0 SDOT (indexed)32-bit
10 1 UDOT (indexed)32-bit
11 0 SDOT (indexed)64-bit
11 1 UDOT (indexed)64-bit

SVE mixed sign dot product (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc00011UZnZda
Decode fields Instruction Details
size U
0x UNALLOCATED
10 0 USDOT (indexed)
10 1 SUDOT
11 UNALLOCATED

SVE Misc

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01000101010op0
Decode fields Instruction details
op0
00xx UNALLOCATED
010x UNALLOCATED
0110 SVE integer matrix multiply accumulate
0111 UNALLOCATED
1xxx UNALLOCATED

SVE integer matrix multiply accumulate

These instructions are under SVE Misc.

313029282726252423222120191817161514131211109876543210
01000101uns0Zm100110ZnZd
Decode fields Instruction Details
uns
00 SMMLA
01 UNALLOCATED
10 USMMLA
11 UMMLA

SVE floating-point convert precision odd elements

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100opc0010opc2101PgZnZd
Decode fields Instruction Details
opc opc2
0x UNALLOCATED
10 0x UNALLOCATED
10 10 BFCVTNT
10 11 UNALLOCATED
11 UNALLOCATED

SVE floating-point multiply-add (indexed)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100size1opc00000opZnZda

SVE floating-point complex multiply-add (indexed)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100size1opc0001rotZnZda
Decode fields Instruction Details
size
0x UNALLOCATED
10 FCMLA (indexed)half-precision
11 FCMLA (indexed)single-precision

SVE floating-point multiply (indexed)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100size1opc001000ZnZd
Decode fields Instruction Details
size
0x FMUL (indexed)half-precision
10 FMUL (indexed)single-precision
11 FMUL (indexed)double-precision

SVE Floating Point Widening Multiply-Add - Indexed

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100op0101op10op2
Decode fields Instruction details
op0op1op2
0 0 00 SVE BFloat16 floating-point dot product (indexed)
0 0 != 00 UNALLOCATED
0 1 UNALLOCATED
1 SVE floating-point multiply-add long (indexed)

SVE floating-point multiply-add long (indexed)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
011001001o21i3hZm01op0i3lTZnZda
Decode fields Instruction Details
o2 op T
0 UNALLOCATED
1 0 0 BFMLALB (indexed)
1 0 1 BFMLALT (indexed)
1 1 UNALLOCATED

SVE BFloat16 floating-point dot product (indexed)

These instructions are under SVE Floating Point Widening Multiply-Add - Indexed.

313029282726252423222120191817161514131211109876543210
011001000op1i2Zm010000ZnZda
Decode fields Instruction Details
op
0 UNALLOCATED
1 BFDOT (indexed)

SVE floating-point multiply-add long (indexed)

These instructions are under SVE Floating Point Widening Multiply-Add - Indexed.

313029282726252423222120191817161514131211109876543210
011001001o21i3hZm01op0i3lTZnZda
Decode fields Instruction Details
o2 op T
0 UNALLOCATED
1 0 0 BFMLALB (indexed)
1 0 1 BFMLALT (indexed)
1 1 UNALLOCATED

SVE Floating Point Widening Multiply-Add

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100op0110op100op2
Decode fields Instruction details
op0op1op2
0 0 0 SVE BFloat16 floating-point dot product
0 0 1 UNALLOCATED
0 1 UNALLOCATED
1 SVE floating-point multiply-add long

SVE floating-point multiply-add long

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
011001001o21Zm10op00TZnZda
Decode fields Instruction Details
o2 op T
0 UNALLOCATED
1 0 0 BFMLALB (vectors)
1 0 1 BFMLALT (vectors)
1 1 UNALLOCATED

SVE BFloat16 floating-point dot product

These instructions are under SVE Floating Point Widening Multiply-Add.

313029282726252423222120191817161514131211109876543210
011001000op1Zm100000ZnZda
Decode fields Instruction Details
op
0 UNALLOCATED
1 BFDOT (vectors)

SVE floating-point multiply-add long

These instructions are under SVE Floating Point Widening Multiply-Add.

313029282726252423222120191817161514131211109876543210
011001001o21Zm10op00TZnZda
Decode fields Instruction Details
o2 op T
0 UNALLOCATED
1 0 0 BFMLALB (vectors)
1 0 1 BFMLALT (vectors)
1 1 UNALLOCATED

SVE floating point matrix multiply accumulate

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100opc1Zm111001ZnZda
Decode fields Instruction Details
opc
00 UNALLOCATED
01 BFMMLA
10 FMMLA32-bit element
11 FMMLA64-bit element

SVE floating-point compare vectors

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100101size0Zmop1o2PgZno3Pd
Decode fields Instruction Details
op o2 o3
0 0 0 FCM<cc> (vectors)FCMGE
0 0 1 FCM<cc> (vectors)FCMGT
0 1 0 FCM<cc> (vectors)FCMEQ
0 1 1 FCM<cc> (vectors)FCMNE
1 0 0 FCM<cc> (vectors)FCMUO
1 0 1 FAC<cc>FACGE
1 1 0 UNALLOCATED
1 1 1 FAC<cc>FACGT

SVE floating-point arithmetic (unpredicated)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100101size0Zm000opcZnZd
Decode fields Instruction Details
opc
000 FADD (vectors, unpredicated)
001 FSUB (vectors, unpredicated)
010 FMUL (vectors, unpredicated)
011 FTSMUL
10x UNALLOCATED
110 FRECPS
111 FRSQRTS

SVE Floating Point Arithmetic - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
011001010op0100op1op2
Decode fields Instruction details
op0op1op2
0x SVE floating-point arithmetic (predicated)
10 000 FTMAD
10 != 000 UNALLOCATED
11 0000 SVE floating-point arithmetic with immediate (predicated)
11 != 0000 UNALLOCATED

SVE floating-point arithmetic (predicated)

These instructions are under SVE Floating Point Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
01100101size00opc100PgZmZdn
Decode fields Instruction Details
opc
0000 FADD (vectors, predicated)
0001 FSUB (vectors, predicated)
0010 FMUL (vectors, predicated)
0011 FSUBR (vectors)
0100 FMAXNM (vectors)
0101 FMINNM (vectors)
0110 FMAX (vectors)
0111 FMIN (vectors)
1000 FABD
1001 FSCALE
1010 FMULX
1011 UNALLOCATED
1100 FDIVR
1101 FDIV
111x UNALLOCATED

SVE floating-point arithmetic with immediate (predicated)

These instructions are under SVE Floating Point Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
01100101size011opc100Pg0000i1Zdn

SVE Floating Point Unary Operations - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
011001010op0101

SVE floating-point round to integral value

These instructions are under SVE Floating Point Unary Operations - Predicated.

313029282726252423222120191817161514131211109876543210
01100101size000opc101PgZnZd

SVE floating-point convert precision

These instructions are under SVE Floating Point Unary Operations - Predicated.

313029282726252423222120191817161514131211109876543210
01100101opc0010opc2101PgZnZd

SVE floating-point unary operations

These instructions are under SVE Floating Point Unary Operations - Predicated.

313029282726252423222120191817161514131211109876543210
01100101size0011opc101PgZnZd
Decode fields Instruction Details
opc
00 FRECPX
01 FSQRT
1x UNALLOCATED

SVE integer convert to floating-point

These instructions are under SVE Floating Point Unary Operations - Predicated.

313029282726252423222120191817161514131211109876543210
01100101opc010opc2U101PgZnZd
Decode fields Instruction Details
opc opc2 U
00 UNALLOCATED
01 00 UNALLOCATED
01 01 0 SCVTF16-bit to half-precision
01 01 1 UCVTF16-bit to half-precision
01 10 0 SCVTF32-bit to half-precision
01 10 1 UCVTF32-bit to half-precision
01 11 0 SCVTF64-bit to half-precision
01 11 1 UCVTF64-bit to half-precision
10 0x UNALLOCATED
10 10 0 SCVTF32-bit to single-precision
10 10 1 UCVTF32-bit to single-precision
10 11 UNALLOCATED
11 00 0 SCVTF32-bit to double-precision
11 00 1 UCVTF32-bit to double-precision
11 01 UNALLOCATED
11 10 0 SCVTF64-bit to single-precision
11 10 1 UCVTF64-bit to single-precision
11 11 0 SCVTF64-bit to double-precision
11 11 1 UCVTF64-bit to double-precision

SVE floating-point convert to integer

These instructions are under SVE Floating Point Unary Operations - Predicated.

313029282726252423222120191817161514131211109876543210
01100101opc011opc2U101PgZnZd
Decode fields Instruction Details
opc opc2 U
00 UNALLOCATED
01 00 UNALLOCATED
01 01 0 FCVTZShalf-precision to 16-bit
01 01 1 FCVTZUhalf-precision to 16-bit
01 10 0 FCVTZShalf-precision to 32-bit
01 10 1 FCVTZUhalf-precision to 32-bit
01 11 0 FCVTZShalf-precision to 64-bit
01 11 1 FCVTZUhalf-precision to 64-bit
10 0x UNALLOCATED
10 10 0 FCVTZSsingle-precision to 32-bit
10 10 1 FCVTZUsingle-precision to 32-bit
10 11 UNALLOCATED
11 00 0 FCVTZSdouble-precision to 32-bit
11 00 1 FCVTZUdouble-precision to 32-bit
11 01 UNALLOCATED
11 10 0 FCVTZSsingle-precision to 64-bit
11 10 1 FCVTZUsingle-precision to 64-bit
11 11 0 FCVTZSdouble-precision to 64-bit
11 11 1 FCVTZUdouble-precision to 64-bit

SVE floating-point recursive reduction

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100101size000opc001PgZnVd
Decode fields Instruction Details
opc
000 FADDV
001 UNALLOCATED
01x UNALLOCATED
100 FMAXNMV
101 FMINNMV
110 FMAXV
111 FMINV

SVE Floating Point Unary Operations - Unpredicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
011001010010011op0
Decode fields Instruction details
op0
00 SVE floating-point reciprocal estimate (unpredicated)
!= 00 UNALLOCATED

SVE floating-point reciprocal estimate (unpredicated)

These instructions are under SVE Floating Point Unary Operations - Unpredicated.

313029282726252423222120191817161514131211109876543210
01100101size001opc001100ZnZd
Decode fields Instruction Details
opc
0xx UNALLOCATED
10x UNALLOCATED
110 FRECPE
111 FRSQRTE

SVE Floating Point Compare - with Zero

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100101010op0001
Decode fields Instruction details
op0
0 SVE floating-point compare with zero
1 UNALLOCATED

SVE floating-point compare with zero

These instructions are under SVE Floating Point Compare - with Zero.

313029282726252423222120191817161514131211109876543210
01100101size0100eqlt001PgZnnePd
Decode fields Instruction Details
eq lt ne
0 0 0 FCM<cc> (zero)FCMGE
0 0 1 FCM<cc> (zero)FCMGT
0 1 0 FCM<cc> (zero)FCMLT
0 1 1 FCM<cc> (zero)FCMLE
1 1 UNALLOCATED
1 0 0 FCM<cc> (zero)FCMEQ
1 1 0 FCM<cc> (zero)FCMNE

SVE floating-point serial reduction (predicated)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100101size011opc001PgZmVdn
Decode fields Instruction Details
opc
000 FADDA
001 UNALLOCATED
01x UNALLOCATED
1xx UNALLOCATED

SVE Floating Point Multiply-Add

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
011001011op0

SVE floating-point multiply-accumulate writing addend

These instructions are under SVE Floating Point Multiply-Add.

313029282726252423222120191817161514131211109876543210
01100101size1Zm0opcPgZnZda
Decode fields Instruction Details
opc
00 FMLA (vectors)
01 FMLS (vectors)
10 FNMLA
11 FNMLS

SVE floating-point multiply-accumulate writing multiplicand

These instructions are under SVE Floating Point Multiply-Add.

313029282726252423222120191817161514131211109876543210
01100101size1Za1opcPgZmZdn
Decode fields Instruction Details
opc
00 FMAD
01 FMSB
10 FNMAD
11 FNMSB

SVE Memory - 32-bit Gather and Unsized Contiguous

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
1000010op0op1op2op3

SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
100001000xs1Zm0mszPgRn0prfop

SVE 32-bit gather load halfwords (scalar plus 32-bit scaled offsets)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
100001001xs1Zm0UffPgRnZt

SVE 32-bit gather load words (scalar plus 32-bit scaled offsets)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
100001010xs1Zm0UffPgRnZt
Decode fields Instruction Details
U ff
0 UNALLOCATED
1 0 LD1W (scalar plus vector)
1 1 LDFF1W (scalar plus vector)

SVE contiguous prefetch (scalar plus immediate)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010111imm60mszPgRn0prfop

SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010!= 11xs0Zm0UffPgRnZt
opc

The following constraints also apply to this encoding: opc != 11 && opc != 11


SVE contiguous prefetch (scalar plus scalar)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010msz00Rm110PgRn0prfop

SVE 32-bit gather prefetch (vector plus immediate)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010msz00imm5111PgZn0prfop

SVE 32-bit gather load (vector plus immediate)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010msz01imm51UffPgZnZt

SVE load and broadcast element

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010dtypeh1imm61dtypelPgRnZt
Decode fields Instruction Details
dtypeh dtypel
00 00 LD1RB8-bit element
00 01 LD1RB16-bit element
00 10 LD1RB32-bit element
00 11 LD1RB64-bit element
01 00 LD1RSW
01 01 LD1RH16-bit element
01 10 LD1RH32-bit element
01 11 LD1RH64-bit element
10 00 LD1RSH64-bit element
10 01 LD1RSH32-bit element
10 10 LD1RW32-bit element
10 11 LD1RW64-bit element
11 00 LD1RSB64-bit element
11 01 LD1RSB32-bit element
11 10 LD1RSB16-bit element
11 11 LD1RD

SVE Memory - Contiguous Load

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
1010010op0op1op2

SVE contiguous non-temporal load (scalar plus immediate)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010msz000imm4111PgRnZt

SVE contiguous non-temporal load (scalar plus scalar)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010msz00Rm110PgRnZt

SVE load multiple structures (scalar plus immediate)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010msz!= 000imm4111PgRnZt
opc

The following constraints also apply to this encoding: opc != 00 && opc != 00


SVE load multiple structures (scalar plus scalar)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010msz!= 00Rm110PgRnZt
opc

The following constraints also apply to this encoding: opc != 00 && opc != 00


SVE load and broadcast quadword (scalar plus immediate)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010mszssz0imm4001PgRnZt


SVE contiguous non-fault load (scalar plus immediate)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010dtype1imm4101PgRnZt
Decode fields Instruction Details
dtype
0000 LDNF1B8-bit element
0001 LDNF1B16-bit element
0010 LDNF1B32-bit element
0011 LDNF1B64-bit element
0100 LDNF1SW
0101 LDNF1H16-bit element
0110 LDNF1H32-bit element
0111 LDNF1H64-bit element
1000 LDNF1SH64-bit element
1001 LDNF1SH32-bit element
1010 LDNF1W32-bit element
1011 LDNF1W64-bit element
1100 LDNF1SB64-bit element
1101 LDNF1SB32-bit element
1110 LDNF1SB16-bit element
1111 LDNF1D

SVE load and broadcast quadword (scalar plus scalar)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010mszsszRm000PgRnZt



SVE Memory - 64-bit Gather

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
1100010op0op1op2op3

SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)

These instructions are under SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
11000100011Zm1mszPgRn0prfop

SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)

These instructions are under SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
110001000xs1Zm0mszPgRn0prfop

SVE 64-bit gather load (scalar plus 64-bit scaled offsets)

These instructions are under SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010!= 0011Zm1UffPgRnZt
opc

The following constraints also apply to this encoding: opc != 00 && opc != 00


SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)

These instructions are under SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010!= 00xs1Zm0UffPgRnZt
opc

The following constraints also apply to this encoding: opc != 00 && opc != 00


SVE 64-bit gather prefetch (vector plus immediate)

These instructions are under SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010msz00imm5111PgZn0prfop

SVE 64-bit gather load (vector plus immediate)

These instructions are under SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010msz01imm51UffPgZnZt

SVE 64-bit gather load (scalar plus 64-bit unscaled offsets)

These instructions are under SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010msz10Zm1UffPgRnZt

SVE 64-bit gather load (scalar plus unpacked 32-bit unscaled offsets)

These instructions are under SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010mszxs0Zm0UffPgRnZt

SVE Memory - Contiguous Store and Unsized Contiguous

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
1110010op00op10op2
Decode fields Instruction details
op0op1op2
0xx 0 UNALLOCATED
10x 0 UNALLOCATED
110 0 0 STR (predicate)
110 0 1 UNALLOCATED
110 1 STR (vector)
111 0 UNALLOCATED
!= 110 1 SVE contiguous store (scalar plus scalar)

SVE contiguous store (scalar plus scalar)

These instructions are under SVE Memory - Contiguous Store and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1110010!= 110o2Rm010PgRnZt
opc

The following constraints also apply to this encoding: opc != 110 && opc != 110

Decode fields Instruction Details
opc o2
00x ST1B (scalar plus scalar)
01x ST1H (scalar plus scalar)
10x ST1W (scalar plus scalar)
111 0 UNALLOCATED
111 1 ST1D (scalar plus scalar)

SVE Memory - Non-temporal and Multi-register Store

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
1110010op00op11

SVE contiguous non-temporal store (scalar plus scalar)

These instructions are under SVE Memory - Non-temporal and Multi-register Store.

313029282726252423222120191817161514131211109876543210
1110010msz00Rm011PgRnZt

SVE store multiple structures (scalar plus scalar)

These instructions are under SVE Memory - Non-temporal and Multi-register Store.

313029282726252423222120191817161514131211109876543210
1110010msz!= 00Rm011PgRnZt
opc

The following constraints also apply to this encoding: opc != 00 && opc != 00


SVE Memory - Scatter with Optional Sign Extend

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
1110010op010

SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offsets)

These instructions are under SVE Memory - Scatter with Optional Sign Extend.

313029282726252423222120191817161514131211109876543210
1110010msz00Zm1xs0PgRnZt

SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offsets)

These instructions are under SVE Memory - Scatter with Optional Sign Extend.

313029282726252423222120191817161514131211109876543210
1110010msz01Zm1xs0PgRnZt
Decode fields Instruction Details
msz
00 UNALLOCATED
01 ST1H (scalar plus vector)
10 ST1W (scalar plus vector)
11 ST1D (scalar plus vector)

SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)

These instructions are under SVE Memory - Scatter with Optional Sign Extend.

313029282726252423222120191817161514131211109876543210
1110010msz10Zm1xs0PgRnZt
Decode fields Instruction Details
msz
00 ST1B (scalar plus vector)
01 ST1H (scalar plus vector)
10 ST1W (scalar plus vector)
11 UNALLOCATED

SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)

These instructions are under SVE Memory - Scatter with Optional Sign Extend.

313029282726252423222120191817161514131211109876543210
1110010msz11Zm1xs0PgRnZt
Decode fields Instruction Details
msz
00 UNALLOCATED
01 ST1H (scalar plus vector)
10 ST1W (scalar plus vector)
11 UNALLOCATED

SVE Memory - Scatter

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
1110010op0101

SVE 64-bit scatter store (scalar plus 64-bit unscaled offsets)

These instructions are under SVE Memory - Scatter.

313029282726252423222120191817161514131211109876543210
1110010msz00Zm101PgRnZt

SVE 64-bit scatter store (scalar plus 64-bit scaled offsets)

These instructions are under SVE Memory - Scatter.

313029282726252423222120191817161514131211109876543210
1110010msz01Zm101PgRnZt
Decode fields Instruction Details
msz
00 UNALLOCATED
01 ST1H (scalar plus vector)
10 ST1W (scalar plus vector)
11 ST1D (scalar plus vector)

SVE 64-bit scatter store (vector plus immediate)

These instructions are under SVE Memory - Scatter.

313029282726252423222120191817161514131211109876543210
1110010msz10imm5101PgZnZt

SVE 32-bit scatter store (vector plus immediate)

These instructions are under SVE Memory - Scatter.

313029282726252423222120191817161514131211109876543210
1110010msz11imm5101PgZnZt
Decode fields Instruction Details
msz
00 ST1B (vector plus immediate)
01 ST1H (vector plus immediate)
10 ST1W (vector plus immediate)
11 UNALLOCATED

SVE Memory - Contiguous Store with Immediate Offset

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
1110010op0op1111

SVE contiguous non-temporal store (scalar plus immediate)

These instructions are under SVE Memory - Contiguous Store with Immediate Offset.

313029282726252423222120191817161514131211109876543210
1110010msz001imm4111PgRnZt

SVE store multiple structures (scalar plus immediate)

These instructions are under SVE Memory - Contiguous Store with Immediate Offset.

313029282726252423222120191817161514131211109876543210
1110010msz!= 001imm4111PgRnZt
opc

The following constraints also apply to this encoding: opc != 00 && opc != 00

SVE contiguous store (scalar plus immediate)

These instructions are under SVE Memory - Contiguous Store with Immediate Offset.

313029282726252423222120191817161514131211109876543210
1110010mszsize0imm4111PgRnZt

Data Processing -- Immediate

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
100op0

PC-rel. addressing

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
opimmlo10000immhiRd
Decode fields Instruction Details
op
0 ADR
1 ADRP

Add/subtract (immediate)

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopS100010shimm12RnRd
Decode fields Instruction Details
sf op S
0 0 0 ADD (immediate)32-bit
0 0 1 ADDS (immediate)32-bit
0 1 0 SUB (immediate)32-bit
0 1 1 SUBS (immediate)32-bit
1 0 0 ADD (immediate)64-bit
1 0 1 ADDS (immediate)64-bit
1 1 0 SUB (immediate)64-bit
1 1 1 SUBS (immediate)64-bit

Add/subtract (immediate, with tags)

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopS100011o2uimm6op3uimm4RnRd
Decode fields Instruction Details Architecture Version
sf op S o2
1 UNALLOCATED-
0 0 UNALLOCATED-
1 1 0 UNALLOCATED-
1 0 0 0 ADDGARMv8.5-MemTag
1 1 0 0 SUBGARMv8.5-MemTag

Logical (immediate)

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopc100100NimmrimmsRnRd
Decode fields Instruction Details
sf opc N
0 1 UNALLOCATED
0 00 0 AND (immediate)32-bit
0 01 0 ORR (immediate)32-bit
0 10 0 EOR (immediate)32-bit
0 11 0 ANDS (immediate)32-bit
1 00 AND (immediate)64-bit
1 01 ORR (immediate)64-bit
1 10 EOR (immediate)64-bit
1 11 ANDS (immediate)64-bit

Move wide (immediate)

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopc100101hwimm16Rd
Decode fields Instruction Details
sf opc hw
01 UNALLOCATED
0 1x UNALLOCATED
0 00 0x MOVN32-bit
0 10 0x MOVZ32-bit
0 11 0x MOVK32-bit
1 00 MOVN64-bit
1 10 MOVZ64-bit
1 11 MOVK64-bit

Bitfield

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopc100110NimmrimmsRnRd
Decode fields Instruction Details
sf opc N
11 UNALLOCATED
0 1 UNALLOCATED
0 00 0 SBFM32-bit
0 01 0 BFM32-bit
0 10 0 UBFM32-bit
1 0 UNALLOCATED
1 00 1 SBFM64-bit
1 01 1 BFM64-bit
1 10 1 UBFM64-bit

Extract

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfop21100111No0RmimmsRnRd
Decode fields Instruction Details
sf op21 N o0 imms
x1 UNALLOCATED
00 1 UNALLOCATED
1x UNALLOCATED
0 1xxxxx UNALLOCATED
0 1 UNALLOCATED
0 00 0 0 0xxxxx EXTR32-bit
1 0 UNALLOCATED
1 00 1 0 EXTR64-bit

Branches, Exception Generating and System instructions

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op0101op1op2
Decode fields Instruction details
op0op1op2
010 0xxxxxxxxxxxxx Conditional branch (immediate)
110 00xxxxxxxxxxxx Exception generation
110 01000000110010 11111 Hints
110 01000000110011 Barriers
110 0100000xxx0100 PSTATE
110 0100x01xxxxxxx System instructions
110 0100x1xxxxxxxx System register move
110 1xxxxxxxxxxxxx Unconditional branch (register)
x00 Unconditional branch (immediate)
x01 0xxxxxxxxxxxxx Compare and branch (immediate)
x01 1xxxxxxxxxxxxx Test and branch (immediate)

Conditional branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
0101010o1imm19o0cond
Decode fields Instruction Details
o1 o0
0 0 B.cond
0 1 UNALLOCATED
1 UNALLOCATED

Exception generation

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
11010100opcimm16op2LL
Decode fields Instruction Details Architecture Version
opc op2 LL
001 UNALLOCATED-
01x UNALLOCATED-
1xx UNALLOCATED-
000 000 00 UNALLOCATED-
000 000 01 SVC-
000 000 10 HVC-
000 000 11 SMCArmv8.0-A
001 000 x1 UNALLOCATED-
001 000 00 BRK-
001 000 1x UNALLOCATED-
010 000 x1 UNALLOCATED-
010 000 00 HLT-
010 000 1x UNALLOCATED-
011 000 01 UNALLOCATED-
011 000 1x UNALLOCATED-
100 000 UNALLOCATED-
101 000 00 UNALLOCATED-
101 000 01 DCPS1-
101 000 10 DCPS2-
101 000 11 DCPS3Armv8.0-A
110 000 UNALLOCATED-
111 000 UNALLOCATED-

Hints

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
11010101000000110010CRmop211111
Decode fields Instruction Details Architecture Version
CRm op2
HINT-
0000 000 NOP-
0000 001 YIELD-
0000 010 WFE-
0000 011 WFI-
0000 100 SEV-
0000 101 SEVL-
0000 110 DGHARMv8.0-DGH
0000 111 XPACD, XPACI, XPACLRIARMv8.3-PAuth
0001 000 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZAPACIA1716ARMv8.3-PAuth
0001 010 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZBPACIB1716ARMv8.3-PAuth
0001 100 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZAAUTIA1716ARMv8.3-PAuth
0001 110 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZBAUTIB1716ARMv8.3-PAuth
0010 000 ESBRAS
0010 001 PSB CSYNCSPE
0010 010 TSB CSYNCARMv8.4-Trace
0010 100 CSDB-
0011 000 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZAPACIAZARMv8.3-PAuth
0011 001 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZAPACIASPARMv8.3-PAuth
0011 010 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZBPACIBZARMv8.3-PAuth
0011 011 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZBPACIBSPARMv8.3-PAuth
0011 100 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZAAUTIAZARMv8.3-PAuth
0011 101 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZAAUTIASPARMv8.3-PAuth
0011 110 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZBAUTIBZARMv8.3-PAuth
0011 111 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZBAUTIBSPARMv8.3-PAuth
0100 xx0 BTIARMv8.5-BTI

Barriers

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
11010101000000110011CRmop2Rt
Decode fields Instruction Details
CRm op2 Rt
000 UNALLOCATED
001 UNALLOCATED
010 11111 CLREX
101 11111 DMB
110 11111 ISB
111 != 11111 UNALLOCATED
111 11111 SB
!= 0x00 100 11111 DSB
0000 100 11111 SSBB
0001 011 UNALLOCATED
001x 011 UNALLOCATED
01xx 011 UNALLOCATED
0100 100 11111 PSSBB
1xxx 011 UNALLOCATED

PSTATE

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101010100000op10100CRmop2Rt
Decode fields Instruction Details Architecture Version
op1 op2 Rt
!= 11111 UNALLOCATED-
11111 MSR (immediate)-
000 000 11111 CFINVARMv8.4-CondM
000 001 11111 XAFLAGARMv8.5-CondM
000 010 11111 AXFLAGARMv8.5-CondM

System instructions

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101010100L01op1CRnCRmop2Rt
Decode fields Instruction Details
L
0 SYS
1 SYSL

System register move

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101010100L1o0op1CRnCRmop2Rt
Decode fields Instruction Details
L
0 MSR (register)
1 MRS

Unconditional branch (register)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101011opcop2op3Rnop4
Decode fields Instruction Details Architecture Version
opc op2 op3 Rn op4
!= 11111 UNALLOCATED-
0000 11111 000000 != 00000 UNALLOCATED-
0000 11111 000000 00000 BR-
0000 11111 000001 UNALLOCATED-
0000 11111 000010 != 11111 UNALLOCATED-
0000 11111 000010 11111 BRAA, BRAAZ, BRAB, BRABZkey A, zero modifierARMv8.3-PAuth
0000 11111 000011 != 11111 UNALLOCATED-
0000 11111 000011 11111 BRAA, BRAAZ, BRAB, BRABZkey B, zero modifierARMv8.3-PAuth
0000 11111 0001xx UNALLOCATED-
0000 11111 001xxx UNALLOCATED-
0000 11111 01xxxx UNALLOCATED-
0000 11111 1xxxxx UNALLOCATED-
0001 11111 000000 != 00000 UNALLOCATED-
0001 11111 000000 00000 BLR-
0001 11111 000001 UNALLOCATED-
0001 11111 000010 != 11111 UNALLOCATED-
0001 11111 000010 11111 BLRAA, BLRAAZ, BLRAB, BLRABZkey A, zero modifierARMv8.3-PAuth
0001 11111 000011 != 11111 UNALLOCATED-
0001 11111 000011 11111 BLRAA, BLRAAZ, BLRAB, BLRABZkey B, zero modifierARMv8.3-PAuth
0001 11111 0001xx UNALLOCATED-
0001 11111 001xxx UNALLOCATED-
0001 11111 01xxxx UNALLOCATED-
0001 11111 1xxxxx UNALLOCATED-
0010 11111 000000 != 00000 UNALLOCATED-
0010 11111 000000 00000 RET-
0010 11111 000001 UNALLOCATED-
0010 11111 000010 != 11111 != 11111 UNALLOCATED-
0010 11111 000010 11111 11111 RETAA, RETABRETAAARMv8.3-PAuth
0010 11111 000011 != 11111 != 11111 UNALLOCATED-
0010 11111 000011 11111 11111 RETAA, RETABRETABARMv8.3-PAuth
0010 11111 0001xx UNALLOCATED-
0010 11111 001xxx UNALLOCATED-
0010 11111 01xxxx UNALLOCATED-
0010 11111 1xxxxx UNALLOCATED-
0011 11111 UNALLOCATED-
0100 11111 000000 != 11111 != 00000 UNALLOCATED-
0100 11111 000000 != 11111 00000 UNALLOCATED-
0100 11111 000000 11111 != 00000 UNALLOCATED-
0100 11111 000000 11111 00000 ERET-
0100 11111 000001 UNALLOCATED-
0100 11111 000010 != 11111 != 11111 UNALLOCATED-
0100 11111 000010 != 11111 11111 UNALLOCATED-
0100 11111 000010 11111 != 11111 UNALLOCATED-
0100 11111 000010 11111 11111 ERETAA, ERETABERETAAARMv8.3-PAuth
0100 11111 000011 != 11111 != 11111 UNALLOCATED-
0100 11111 000011 != 11111 11111 UNALLOCATED-
0100 11111 000011 11111 != 11111 UNALLOCATED-
0100 11111 000011 11111 11111 ERETAA, ERETABERETABARMv8.3-PAuth
0100 11111 0001xx UNALLOCATED-
0100 11111 001xxx UNALLOCATED-
0100 11111 01xxxx UNALLOCATED-
0100 11111 1xxxxx UNALLOCATED-
0101 11111 != 000000 UNALLOCATED-
0101 11111 000000 != 11111 != 00000 UNALLOCATED-
0101 11111 000000 != 11111 00000 UNALLOCATED-
0101 11111 000000 11111 != 00000 UNALLOCATED-
0101 11111 000000 11111 00000 DRPS-
011x 11111 UNALLOCATED-
1000 11111 00000x UNALLOCATED-
1000 11111 000010 BRAA, BRAAZ, BRAB, BRABZkey A, register modifierARMv8.3-PAuth
1000 11111 000011 BRAA, BRAAZ, BRAB, BRABZkey B, register modifierARMv8.3-PAuth
1000 11111 0001xx UNALLOCATED-
1000 11111 001xxx UNALLOCATED-
1000 11111 01xxxx UNALLOCATED-
1000 11111 1xxxxx UNALLOCATED-
1001 11111 00000x UNALLOCATED-
1001 11111 000010 BLRAA, BLRAAZ, BLRAB, BLRABZkey A, register modifierARMv8.3-PAuth
1001 11111 000011 BLRAA, BLRAAZ, BLRAB, BLRABZkey B, register modifierARMv8.3-PAuth
1001 11111 0001xx UNALLOCATED-
1001 11111 001xxx UNALLOCATED-
1001 11111 01xxxx UNALLOCATED-
1001 11111 1xxxxx UNALLOCATED-
101x 11111 UNALLOCATED-
11xx 11111 UNALLOCATED-

Unconditional branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
op00101imm26
Decode fields Instruction Details
op
0 B
1 BL

Compare and branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
sf011010opimm19Rt
Decode fields Instruction Details
sf op
0 0 CBZ32-bit
0 1 CBNZ32-bit
1 0 CBZ64-bit
1 1 CBNZ64-bit

Test and branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
b5011011opb40imm14Rt
Decode fields Instruction Details
op
0 TBZ
1 TBNZ

Loads and Stores

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op01op10op2op3op4
Decode fields Instruction details
op0op1op2op3op4
0x00 1 00 000000 Advanced SIMD load/store multiple structures
0x00 1 01 0xxxxx Advanced SIMD load/store multiple structures (post-indexed)
0x00 1 0x 1xxxxx UNALLOCATED
0x00 1 10 x00000 Advanced SIMD load/store single structure
0x00 1 11 Advanced SIMD load/store single structure (post-indexed)
0x00 1 x0 x1xxxx UNALLOCATED
0x00 1 x0 xx1xxx UNALLOCATED
0x00 1 x0 xxx1xx UNALLOCATED
0x00 1 x0 xxxx1x UNALLOCATED
0x00 1 x0 xxxxx1 UNALLOCATED
1101 0 1x 1xxxxx Load/store memory tags
1x00 1 UNALLOCATED
xx00 0 0x Load/store exclusive
xx01 0 1x 0xxxxx 00 LDAPR/STLR (unscaled immediate)
xx01 0x Load register (literal)
xx10 00 Load/store no-allocate pair (offset)
xx10 01 Load/store register pair (post-indexed)
xx10 10 Load/store register pair (offset)
xx10 11 Load/store register pair (pre-indexed)
xx11 0x 0xxxxx 00 Load/store register (unscaled immediate)
xx11 0x 0xxxxx 01 Load/store register (immediate post-indexed)
xx11 0x 0xxxxx 10 Load/store register (unprivileged)
xx11 0x 0xxxxx 11 Load/store register (immediate pre-indexed)
xx11 0x 1xxxxx 00 Atomic memory operations
xx11 0x 1xxxxx 10 Load/store register (register offset)
xx11 0x 1xxxxx x1 Load/store register (pac)
xx11 1x Load/store register (unsigned immediate)

Advanced SIMD load/store multiple structures

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
0Q0011000L000000opcodesizeRnRt
Decode fields Instruction Details
L opcode
0 0000 ST4 (multiple structures)
0 0001 UNALLOCATED
0 0010 ST1 (multiple structures)four registers
0 0011 UNALLOCATED
0 0100 ST3 (multiple structures)
0 0101 UNALLOCATED
0 0110 ST1 (multiple structures)three registers
0 0111 ST1 (multiple structures)one register
0 1000 ST2 (multiple structures)
0 1001 UNALLOCATED
0 1010 ST1 (multiple structures)two registers
0 1011 UNALLOCATED
0 11xx UNALLOCATED
1 0000 LD4 (multiple structures)
1 0001 UNALLOCATED
1 0010 LD1 (multiple structures)four registers
1 0011 UNALLOCATED
1 0100 LD3 (multiple structures)
1 0101 UNALLOCATED
1 0110 LD1 (multiple structures)three registers
1 0111 LD1 (multiple structures)one register
1 1000 LD2 (multiple structures)
1 1001 UNALLOCATED
1 1010 LD1 (multiple structures)two registers
1 1011 UNALLOCATED
1 11xx UNALLOCATED

Advanced SIMD load/store multiple structures (post-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
0Q0011001L0RmopcodesizeRnRt
Decode fields Instruction Details
L Rm opcode
0 0001 UNALLOCATED
0 0011 UNALLOCATED
0 0101 UNALLOCATED
0 1001 UNALLOCATED
0 1011 UNALLOCATED
0 11xx UNALLOCATED
0 != 11111 0000 ST4 (multiple structures)register offset
0 != 11111 0010 ST1 (multiple structures)four registers, register offset
0 != 11111 0100 ST3 (multiple structures)register offset
0 != 11111 0110 ST1 (multiple structures)three registers, register offset
0 != 11111 0111 ST1 (multiple structures)one register, register offset
0 != 11111 1000 ST2 (multiple structures)register offset
0 != 11111 1010 ST1 (multiple structures)two registers, register offset
0 11111 0000 ST4 (multiple structures)immediate offset
0 11111 0010 ST1 (multiple structures)four registers, immediate offset
0 11111 0100 ST3 (multiple structures)immediate offset
0 11111 0110 ST1 (multiple structures)three registers, immediate offset
0 11111 0111 ST1 (multiple structures)one register, immediate offset
0 11111 1000 ST2 (multiple structures)immediate offset
0 11111 1010 ST1 (multiple structures)two registers, immediate offset
1 0001 UNALLOCATED
1 0011 UNALLOCATED
1 0101 UNALLOCATED
1 1001 UNALLOCATED
1 1011 UNALLOCATED
1 11xx UNALLOCATED
1 != 11111 0000 LD4 (multiple structures)register offset
1 != 11111 0010 LD1 (multiple structures)four registers, register offset
1 != 11111 0100 LD3 (multiple structures)register offset
1 != 11111 0110 LD1 (multiple structures)three registers, register offset
1 != 11111 0111 LD1 (multiple structures)one register, register offset
1 != 11111 1000 LD2 (multiple structures)register offset
1 != 11111 1010 LD1 (multiple structures)two registers, register offset
1 11111 0000 LD4 (multiple structures)immediate offset
1 11111 0010 LD1 (multiple structures)four registers, immediate offset
1 11111 0100 LD3 (multiple structures)immediate offset
1 11111 0110 LD1 (multiple structures)three registers, immediate offset
1 11111 0111 LD1 (multiple structures)one register, immediate offset
1 11111 1000 LD2 (multiple structures)immediate offset
1 11111 1010 LD1 (multiple structures)two registers, immediate offset

Advanced SIMD load/store single structure

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
0Q0011010LR00000opcodeSsizeRnRt
Decode fields Instruction Details
L R opcode S size
0 11x UNALLOCATED
0 0 000 ST1 (single structure)8-bit
0 0 001 ST3 (single structure)8-bit
0 0 010 x0 ST1 (single structure)16-bit
0 0 010 x1 UNALLOCATED
0 0 011 x0 ST3 (single structure)16-bit
0 0 011 x1 UNALLOCATED
0 0 100 00 ST1 (single structure)32-bit
0 0 100 1x UNALLOCATED
0 0 100 0 01 ST1 (single structure)64-bit
0 0 100 1 01 UNALLOCATED
0 0 101 00 ST3 (single structure)32-bit
0 0 101 10 UNALLOCATED
0 0 101 0 01 ST3 (single structure)64-bit
0 0 101 0 11 UNALLOCATED
0 0 101 1 x1 UNALLOCATED
0 1 000 ST2 (single structure)8-bit
0 1 001 ST4 (single structure)8-bit
0 1 010 x0 ST2 (single structure)16-bit
0 1 010 x1 UNALLOCATED
0 1 011 x0 ST4 (single structure)16-bit
0 1 011 x1 UNALLOCATED
0 1 100 00 ST2 (single structure)32-bit
0 1 100 10 UNALLOCATED
0 1 100 0 01 ST2 (single structure)64-bit
0 1 100 0 11 UNALLOCATED
0 1 100 1 x1 UNALLOCATED
0 1 101 00 ST4 (single structure)32-bit
0 1 101 10 UNALLOCATED
0 1 101 0 01 ST4 (single structure)64-bit
0 1 101 0 11 UNALLOCATED
0 1 101 1 x1 UNALLOCATED
1 0 000 LD1 (single structure)8-bit
1 0 001 LD3 (single structure)8-bit
1 0 010 x0 LD1 (single structure)16-bit
1 0 010 x1 UNALLOCATED
1 0 011 x0 LD3 (single structure)16-bit
1 0 011 x1 UNALLOCATED
1 0 100 00 LD1 (single structure)32-bit
1 0 100 1x UNALLOCATED
1 0 100 0 01 LD1 (single structure)64-bit
1 0 100 1 01 UNALLOCATED
1 0 101 00 LD3 (single structure)32-bit
1 0 101 10 UNALLOCATED
1 0 101 0 01 LD3 (single structure)64-bit
1 0 101 0 11 UNALLOCATED
1 0 101 1 x1 UNALLOCATED
1 0 110 0 LD1R
1 0 110 1 UNALLOCATED
1 0 111 0 LD3R
1 0 111 1 UNALLOCATED
1 1 000 LD2 (single structure)8-bit
1 1 001 LD4 (single structure)8-bit
1 1 010 x0 LD2 (single structure)16-bit
1 1 010 x1 UNALLOCATED
1 1 011 x0 LD4 (single structure)16-bit
1 1 011 x1 UNALLOCATED
1 1 100 00 LD2 (single structure)32-bit
1 1 100 10 UNALLOCATED
1 1 100 0 01 LD2 (single structure)64-bit
1 1 100 0 11 UNALLOCATED
1 1 100 1 x1 UNALLOCATED
1 1 101 00 LD4 (single structure)32-bit
1 1 101 10 UNALLOCATED
1 1 101 0 01 LD4 (single structure)64-bit
1 1 101 0 11 UNALLOCATED
1 1 101 1 x1 UNALLOCATED
1 1 110 0 LD2R
1 1 110 1 UNALLOCATED
1 1 111 0 LD4R
1 1 111 1 UNALLOCATED

Advanced SIMD load/store single structure (post-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
0Q0011011LRRmopcodeSsizeRnRt
Decode fields Instruction Details
L R Rm opcode S size
0 11x UNALLOCATED
0 0 010 x1 UNALLOCATED
0 0 011 x1 UNALLOCATED
0 0 100 1x UNALLOCATED
0 0 100 1 01 UNALLOCATED
0 0 101 10 UNALLOCATED
0 0 101 0 11 UNALLOCATED
0 0 101 1 x1 UNALLOCATED
0 0 != 11111 000 ST1 (single structure)8-bit, register offset
0 0 != 11111 001 ST3 (single structure)8-bit, register offset
0 0 != 11111 010 x0 ST1 (single structure)16-bit, register offset
0 0 != 11111 011 x0 ST3 (single structure)16-bit, register offset
0 0 != 11111 100 00 ST1 (single structure)32-bit, register offset
0 0 != 11111 100 0 01 ST1 (single structure)64-bit, register offset
0 0 != 11111 101 00 ST3 (single structure)32-bit, register offset
0 0 != 11111 101 0 01 ST3 (single structure)64-bit, register offset
0 0 11111 000 ST1 (single structure)8-bit, immediate offset
0 0 11111 001 ST3 (single structure)8-bit, immediate offset
0 0 11111 010 x0 ST1 (single structure)16-bit, immediate offset
0 0 11111 011 x0 ST3 (single structure)16-bit, immediate offset
0 0 11111 100 00 ST1 (single structure)32-bit, immediate offset
0 0 11111 100 0 01 ST1 (single structure)64-bit, immediate offset
0 0 11111 101 00 ST3 (single structure)32-bit, immediate offset
0 0 11111 101 0 01 ST3 (single structure)64-bit, immediate offset
0 1 010 x1 UNALLOCATED
0 1 011 x1 UNALLOCATED
0 1 100 10 UNALLOCATED
0 1 100 0 11 UNALLOCATED
0 1 100 1 x1 UNALLOCATED
0 1 101 10 UNALLOCATED
0 1 101 0 11 UNALLOCATED
0 1 101 1 x1 UNALLOCATED
0 1 != 11111 000 ST2 (single structure)8-bit, register offset
0 1 != 11111 001 ST4 (single structure)8-bit, register offset
0 1 != 11111 010 x0 ST2 (single structure)16-bit, register offset
0 1 != 11111 011 x0 ST4 (single structure)16-bit, register offset
0 1 != 11111 100 00 ST2 (single structure)32-bit, register offset
0 1 != 11111 100 0 01 ST2 (single structure)64-bit, register offset
0 1 != 11111 101 00 ST4 (single structure)32-bit, register offset
0 1 != 11111 101 0 01 ST4 (single structure)64-bit, register offset
0 1 11111 000 ST2 (single structure)8-bit, immediate offset
0 1 11111 001 ST4 (single structure)8-bit, immediate offset
0 1 11111 010 x0 ST2 (single structure)16-bit, immediate offset
0 1 11111 011 x0 ST4 (single structure)16-bit, immediate offset
0 1 11111 100 00 ST2 (single structure)32-bit, immediate offset
0 1 11111 100 0 01 ST2 (single structure)64-bit, immediate offset
0 1 11111 101 00 ST4 (single structure)32-bit, immediate offset
0 1 11111 101 0 01 ST4 (single structure)64-bit, immediate offset
1 0 010 x1 UNALLOCATED
1 0 011 x1 UNALLOCATED
1 0 100 1x UNALLOCATED
1 0 100 1 01 UNALLOCATED
1 0 101 10 UNALLOCATED
1 0 101 0 11 UNALLOCATED
1 0 101 1 x1 UNALLOCATED
1 0 110 1 UNALLOCATED
1 0 111 1 UNALLOCATED
1 0 != 11111 000 LD1 (single structure)8-bit, register offset
1 0 != 11111 001 LD3 (single structure)8-bit, register offset
1 0 != 11111 010 x0 LD1 (single structure)16-bit, register offset
1 0 != 11111 011 x0 LD3 (single structure)16-bit, register offset
1 0 != 11111 100 00 LD1 (single structure)32-bit, register offset
1 0 != 11111 100 0 01 LD1 (single structure)64-bit, register offset
1 0 != 11111 101 00 LD3 (single structure)32-bit, register offset
1 0 != 11111 101 0 01 LD3 (single structure)64-bit, register offset
1 0 != 11111 110 0 LD1Rregister offset
1 0 != 11111 111 0 LD3Rregister offset
1 0 11111 000 LD1 (single structure)8-bit, immediate offset
1 0 11111 001 LD3 (single structure)8-bit, immediate offset
1 0 11111 010 x0 LD1 (single structure)16-bit, immediate offset
1 0 11111 011 x0 LD3 (single structure)16-bit, immediate offset
1 0 11111 100 00 LD1 (single structure)32-bit, immediate offset
1 0 11111 100 0 01 LD1 (single structure)64-bit, immediate offset
1 0 11111 101 00 LD3 (single structure)32-bit, immediate offset
1 0 11111 101 0 01 LD3 (single structure)64-bit, immediate offset
1 0 11111 110 0 LD1Rimmediate offset
1 0 11111 111 0 LD3Rimmediate offset
1 1 010 x1 UNALLOCATED
1 1 011 x1 UNALLOCATED
1 1 100 10 UNALLOCATED
1 1 100 0 11 UNALLOCATED
1 1 100 1 x1 UNALLOCATED
1 1 101 10 UNALLOCATED
1 1 101 0 11 UNALLOCATED
1 1 101 1 x1 UNALLOCATED
1 1 110 1 UNALLOCATED
1