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## SABD

Signed absolute difference (predicated).

Compute the absolute difference between signed integer values in active elements of the second source vector and corresponding elements of the first source vector and destructively place the difference in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 size 0 0 1 1 0 0 0 0 0 Pg Zm Zdn U

#### SVE

SABD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

```if !HaveSVE() then UNDEFINED;
integer esize = 8 << UInt(size);
integer g = UInt(Pg);
integer dn = UInt(Zdn);
integer m = UInt(Zm);
boolean unsigned = FALSE;```

### Assembler Symbols

 Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.
<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D
 Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 Is the name of the second source scalable vector register, encoded in the "Zm" field.

### Operation

```CheckSVEEnabled();
integer elements = VL DIV esize;
bits(VL) operand1 = Z[dn];
bits(VL) operand2 = Z[m];
bits(VL) result;

for e = 0 to elements-1
integer element1 = Int(Elem[operand1, e, esize], unsigned);
integer element2 = Int(Elem[operand2, e, esize], unsigned);
if ElemP[mask, e, esize] == '1' then
integer absdiff = Abs(element1 - element2);
Elem[result, e, esize] = absdiff<esize-1:0>;
else
Elem[result, e, esize] = Elem[operand1, e, esize];

Z[dn] = result;```

### Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:

• The MOVPRFX instruction must be unpredicated, or be predicated using the same governing predicate register and source element size as this instruction.
• The MOVPRFX instruction must specify the same destination register as this instruction.
• The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.