UXTL, UXTL2
Unsigned extend Long. This instruction copies each vector element from the lower or upper half of the source SIMD&FP register into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.
The UXTL instruction extracts vector elements from the lower half of the source register, while the UXTL2 instruction extracts vector elements from the upper half of the source register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
This is an alias of USHLL, USHLL2. This means:
- The encodings in this description are named to match the encodings of USHLL, USHLL2.
- The description of USHLL, USHLL2 gives the operational pseudocode for this instruction.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Q | 1 | 0 | 1 | 1 | 1 | 1 | 0 | != 0000 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | Rn | Rd | |||||||||||
U | immh | immb |
Vector
is equivalent to
USHLL{2} <Vd>.<Ta>, <Vn>.<Tb>, #0
and is the preferred disassembly when BitCount(immh) == 1.
Assembler Symbols
<Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Ta> |
Is an arrangement specifier,
encoded in
immh:
|
<Vn> |
Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
<Tb> |
Is an arrangement specifier,
encoded in
immh:Q:
|
Operation
The description of USHLL, USHLL2 gives the operational pseudocode for this instruction.
Operational information
If PSTATE.DIT is 1:
- The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.