MOV (immediate, predicated, merging)
Move signed integer immediate to vector elements (merging).
Move a signed integer immediate to each active element in the destination vector. Inactive elements in the destination vector register remain unmodified.
The immediate operand is a signed value in the range -128 to +127, and for element widths of 16 bits or higher it may also be a signed multiple of 256 in the range -32768 to +32512 (excluding 0).
The immediate is encoded in 8 bits with an optional left shift by 8. The preferred disassembly when the shift option is specified is "#<simm8>, LSL #8". However an assembler and disassembler may also allow use of the shifted 16-bit value unless the immediate is 0 and the shift amount is 8, which must be unambiguously described as "#0, LSL #8".
This is an alias of CPY (immediate, merging). This means:
- The encodings in this description are named to match the encodings of CPY (immediate, merging).
- The description of CPY (immediate, merging) gives the operational pseudocode for this instruction.
is equivalent to
and is always the preferred disassembly.
Is the name of the destination scalable vector register, encoded in the "Zd" field.
Is the size specifier,
Is the name of the governing scalable predicate register, encoded in the "Pg" field.
Is a signed immediate in the range -128 to 127, encoded in the "imm8" field.
Is the optional left shift to apply to the immediate, defaulting to LSL #0 and
The description of CPY (immediate, merging) gives the operational pseudocode for this instruction.
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:
- The MOVPRFX instruction must be unpredicated, or be predicated using the same governing predicate register and source element size as this instruction.
- The MOVPRFX instruction must specify the same destination register as this instruction.
- The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.