## ST4W (scalar plus immediate)

Contiguous store four-word structures from four vectors (immediate index).

Contiguous store four-word structures, each from the same element number in four vector registers to the memory address generated by a 64-bit scalar base and an immediate index which is a multiple of 4 in the range -32 to 28 that is multiplied by the vector's in-memory size, irrespective of predication,

Each predicate element applies to the same element number in each of the four vector registers, or equivalently to the four consecutive words in memory which make up each structure. Inactive structures are not written to memory.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |

1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | imm4 | 1 | 1 | 1 | Pg | Rn | Zt | |||||||||||||

msz<1> | msz<0> |

if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer g = UInt(Pg); integer esize = 32; integer offset = SInt(imm4); integer nreg = 4;

### Assembler Symbols

<Zt1> |
Is the name of the first scalable vector register to be transferred, encoded in the "Zt" field. |

<Zt2> |
Is the name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32. |

<Zt3> |
Is the name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32. |

<Zt4> |
Is the name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32. |

<Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |

<Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |

<imm> |
Is the optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field. |

### Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(64) base; bits(64) addr; bits(PL) mask = P[g]; constant integer mbytes = esize DIV 8; array [0..3] of bits(VL) values; if n == 31 then if LastActiveElement(mask, esize) >= 0 || ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); if HaveMTEExt() then SetTagCheckedInstruction(FALSE); base = SP[]; else if HaveMTEExt() then SetTagCheckedInstruction(TRUE); base = X[n]; for r = 0 to nreg-1 values[r] = Z[(t+r) MOD 32]; addr = base + offset * elements * nreg * mbytes; for e = 0 to elements-1 for r = 0 to nreg-1 if ElemP[mask, e, esize] == '1' then Mem[addr, mbytes, AccType_NORMAL] = Elem[values[r], e, esize]; addr = addr + mbytes;