ZIP1, ZIP2 (vectors)
Interleave elements from two half vectors.
Interleave alternating elements from the lowest or highest halves of the first and second source vectors and place in elements of the destination vector. This instruction is unpredicated. The 128-bit element variant of this instruction requires that the current vector length is at least 256 bits, and if the current vector length is not an integer multiple of 256 bits then the trailing bits are set to zero.
ID_AA64ZFR0_EL1.F64MM indicates whether the 128-bit element variant of the instruction is implemented.
It has encodings from 4 classes:
High halves
,
High halves (quadwords)
,
Low halves
and
Low halves (quadwords)
High halves
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | size | 1 | Zm | 0 | 1 | 1 | 0 | 0 | 1 | Zn | Zd |
| | | | | | H | | |
if !HaveSVE() then UNDEFINED;
integer esize = 8 << UInt(size);
integer n = UInt(Zn);
integer m = UInt(Zm);
integer d = UInt(Zd);
integer part = 1;
High halves (quadwords)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | Zm | 0 | 0 | 0 | 0 | 0 | 1 | Zn | Zd |
| | | | | | H | | |
if !HaveSVEFP64MatMulExt() then UNDEFINED;
integer esize = 128;
integer n = UInt(Zn);
integer m = UInt(Zm);
integer d = UInt(Zd);
integer part = 1;
Low halves
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | size | 1 | Zm | 0 | 1 | 1 | 0 | 0 | 0 | Zn | Zd |
| | | | | | H | | |
if !HaveSVE() then UNDEFINED;
integer esize = 8 << UInt(size);
integer n = UInt(Zn);
integer m = UInt(Zm);
integer d = UInt(Zd);
integer part = 0;
Low halves (quadwords)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | Zm | 0 | 0 | 0 | 0 | 0 | 0 | Zn | Zd |
| | | | | | H | | |
if !HaveSVEFP64MatMulExt() then UNDEFINED;
integer esize = 128;
integer n = UInt(Zn);
integer m = UInt(Zm);
integer d = UInt(Zd);
integer part = 0;
Assembler Symbols
<Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field.
|
<T> |
Is the size specifier,
encoded in
size :
size |
<T> |
00 |
B |
01 |
H |
10 |
S |
11 |
D |
|
<Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field.
|
<Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field.
|
Operation
CheckSVEEnabled();
if VL < esize * 2 then UNDEFINED;
integer pairs = VL DIV (esize * 2);
bits(VL) operand1 = Z[n];
bits(VL) operand2 = Z[m];
bits(VL) result = Zeros();
integer base = part * pairs;
for p = 0 to pairs-1
Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
Z[d] = result;