You copied the Doc URL to your clipboard.


Load Tag Multiple reads a naturally aligned block of N Allocation Tags, where the size of N is identified in GMID_EL1.BS, and writes the Allocation Tag read from address A to the destination register at 4*A<7:4>+3:4*A<7:4>. Bits of the destination register not written with an Allocation Tag are set to 0.

This instruction is undefined at EL0.

This instruction generates an Unchecked access.

If ID_AA64PFR1_EL1.MTE != 0b0010, this instruction is undefined.



LDGM <Xt>, [<Xn|SP>]

if !HaveMTEExt() then UNDEFINED;
integer t = UInt(Xt);
integer n = UInt(Xn);

Assembler Symbols


Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Xt" field.


Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Xn" field.


if PSTATE.EL == EL0 then

bits(64) data = Zeros(64);
bits(64) address;

if n == 31 then
    address = SP[];
    address = X[n];

integer size = 4 * (2 ^ (UInt(GMID_EL1.BS)));
address = Align(address, size);
integer count = size >> LOG2_TAG_GRANULE;
integer index = UInt(address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE>);

for i = 0 to count-1
    bits(4) tag = AArch64.MemTag[address, AccType_NORMAL];
    data<(index*4)+3:index*4> = tag;
    address = address + TAG_GRANULE;
    index = index + 1;

X[t] = data;