Prefetch Memory (register) signals the memory system that data memory accesses from a specified address are likely to occur in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as preloading the cache line containing the specified address into one or more caches.
The effect of an PRFM instruction is implementation defined. For more information, see Prefetch memory.
For information about memory accesses, see Load/Store addressing modes.
if option<1> == '0' then UNDEFINED; // sub-word index ExtendType extend_type = DecodeRegExtend(option); integer shift = if S == '1' then 3 else 0;
Is the prefetch operation, defined as <type><target><policy>.
<type> is one of:
<target> is one of:
<policy> is one of:
For more information on these prefetch operations, see Prefetch memory.
For other encodings of the "Rt" field, use <imm5>.
Is the prefetch operation encoding as an immediate, in the range 0 to 31, encoded in the "Rt" field.
This syntax is only for encodings that are not accessible using <prfop>.
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
When option<0> is set to 0, is the 32-bit name of the general-purpose index register, encoded in the "Rm" field.
When option<0> is set to 1, is the 64-bit name of the general-purpose index register, encoded in the "Rm" field.
Is the index extend/shift specifier, defaulting to LSL, and which must be omitted for the LSL option when <amount> is omitted.
Is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is