MOV (to general)
Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
This is an alias of UMOV. This means:
- The encodings in this description are named to match the encodings of UMOV.
- The description of UMOV gives the operational pseudocode for this instruction.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | x | x | x | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | Rn | Rd | ||||||||
imm5 |
32-bit (Q == 0 && imm5 == xx100)
is equivalent to
and is always the preferred disassembly.
64-reg,UMOV-64-reg (Q == 1 && imm5 == x1000)
is equivalent to
and is always the preferred disassembly.
Assembler Symbols
<Wd> |
Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Xd> |
Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Vn> |
Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
<index> |
For the 32-bit variant: is the element index encoded in "imm5<4:3>". |
For the 64-reg,UMOV-64-reg variant: is the element index encoded in "imm5<4>". |
Operation
The description of UMOV gives the operational pseudocode for this instruction.
Operational information
If PSTATE.DIT is 1:
- The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.