You copied the Doc URL to your clipboard.
SHA1H
SHA1 fixed rotate.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | Rn | Rd |
integer d = UInt(Rd); integer n = UInt(Rn); if !HaveSHA1Ext() then UNDEFINED;
Assembler Symbols
<Sd> |
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Sn> |
Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
Operation
AArch64.CheckFPAdvSIMDEnabled(); bits(32) operand = V[n]; // read element [0] only, [1-3] zeroed V[d] = ROL(operand, 30);
Operational information
If PSTATE.DIT is 1:
- The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.