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## URSHL

Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Scalar and Vector

### Scalar

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 1 1 1 0 size 1 Rm 0 1 0 1 0 1 Rn Rd U R S
integer d = UInt(Rd);
integer n = UInt(Rn);
integer m = UInt(Rm);
integer esize = 8 << UInt(size);
integer datasize = esize;
integer elements = 1;
boolean unsigned = (U == '1');
boolean rounding = (R == '1');
boolean saturating = (S == '1');
if S == '0' && size != '11' then UNDEFINED;

### Vector

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 Q 1 0 1 1 1 0 size 1 Rm 0 1 0 1 0 1 Rn Rd U R S
integer d = UInt(Rd);
integer n = UInt(Rn);
integer m = UInt(Rm);
if size:Q == '110' then UNDEFINED;
integer esize = 8 << UInt(size);
integer datasize = if Q == '1' then 128 else 64;
integer elements = datasize DIV esize;
boolean unsigned = (U == '1');
boolean rounding = (R == '1');
boolean saturating = (S == '1');

### Assembler Symbols

<V> Is a width specifier, encoded in size:
size <V>
0x RESERVED
10 RESERVED
11 D
 Is the number of the SIMD&FP destination register, in the "Rd" field.
 Is the number of the first SIMD&FP source register, encoded in the "Rn" field.
 Is the number of the second SIMD&FP source register, encoded in the "Rm" field.
 Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T> Is an arrangement specifier, encoded in size:Q:
size Q <T>
00 0 8B
00 1 16B
01 0 4H
01 1 8H
10 0 2S
10 1 4S
11 0 RESERVED
11 1 2D
 Is the name of the first SIMD&FP source register, encoded in the "Rn" field.
 Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

### Operation

bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;

integer round_const = 0;
integer shift;
integer element;
boolean sat;

for e = 0 to elements-1
shift = SInt(Elem[operand2, e, esize]<7:0>);
if rounding then
round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift
element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
if saturating then
(Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
if sat then FPSR.QC = '1';
else
Elem[result, e, esize] = element<esize-1:0>;

V[d] = result;