You copied the Doc URL to your clipboard.

FDIV (scalar)

Floating-point Divide (scalar). This instruction divides the floating-point value of the first source SIMD&FP register by the floating-point value of the second source SIMD&FP register, and writes the result to the destination SIMD&FP register.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

313029282726252423222120191817161514131211109876543210
00011110ftype1Rm000110RnRd

Half-precision (ftype == 11)
(Armv8.2)

FDIV <Hd>, <Hn>, <Hm>

Single-precision (ftype == 00)

FDIV <Sd>, <Sn>, <Sm>

Double-precision (ftype == 01)

FDIV <Dd>, <Dn>, <Dm>

integer d = UInt(Rd);
integer n = UInt(Rn);
integer m = UInt(Rm);

integer esize;
case ftype of
    when '00' esize = 32;
    when '01' esize = 64;
    when '10' UNDEFINED;
    when '11'
        if HaveFP16Ext() then
            esize = 16;
        else
            UNDEFINED;

Assembler Symbols

<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Dn>

Is the 64-bit name of the first SIMD&FP source register, encoded in the "Rn" field.

<Dm>

Is the 64-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

<Hd>

Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Hn>

Is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.

<Hm>

Is the 16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

<Sd>

Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Sn>

Is the 32-bit name of the first SIMD&FP source register, encoded in the "Rn" field.

<Sm>

Is the 32-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

Operation

CheckFPAdvSIMDEnabled64();
bits(esize) operand1 = V[n];
bits(esize) operand2 = V[m];

FPCRType fpcr = FPCR[];
boolean merge = IsMerging(fpcr);
bits(128) result = if merge then V[n] else Zeros();

Elem[result, 0, esize] = FPDiv(operand1, operand2, FPCR[]);

V[d] = result;