You copied the Doc URL to your clipboard.

TSB CSYNC

Trace Synchronization Barrier. This instruction is a barrier that synchronizes the trace operations of instructions.

If ARMv8.4-Trace is not implemented, this instruction executes as a NOP.

System
(Armv8.4)

313029282726252423222120191817161514131211109876543210
11010101000000110010001001011111
CRmop2

System

TSB CSYNC

if !HaveSelfHostedTrace() then EndOfInstruction();

Was this page helpful? Yes No