LDREXD
Load Register Exclusive Doubleword derives an address from a base register value, loads a 64-bit doubleword from memory, writes it to two registers and:
- If the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing PE in a global monitor.
- Causes the executing PE to indicate an active exclusive access in the local monitor.
For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
A1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | Rn | Rt | (1) | (1) | 1 | 1 | 1 | 0 | 0 | 1 | (1) | (1) | (1) | (1) | |||||||||
cond |
t = UInt(Rt); t2 = t + 1; n = UInt(Rn); if Rt<0> == '1' || t2 == 15 || n == 15 then UNPREDICTABLE;
CONSTRAINED UNPREDICTABLE behavior
If Rt<0> == '1', then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The instruction executes with the additional decode: t<0> = '0'.
- The instruction executes with the additional decode: t2 = t.
- The instruction executes as described, with no change to its behavior and no additional side effects.
If Rt == '1110', then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The instruction is handled as described in Using R15.
T1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | Rn | Rt | Rt2 | 0 | 1 | 1 | 1 | (1) | (1) | (1) | (1) |
t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); if t == 15 || t2 == 15 || t == t2 || n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13
CONSTRAINED UNPREDICTABLE behavior
If t == t2, then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The load instruction executes but the destination register takes an unknown value.
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
Assembler Symbols
<c> |
<q> |
<Rn> |
Is the general-purpose base register, encoded in the "Rn" field. |
Operation
if ConditionPassed() then EncodingSpecificOperations(); address = R[n]; AArch32.SetExclusiveMonitors(address,8); value = MemA[address,8]; // Extract words from 64-bit loaded value such that R[t] is // loaded from address and R[t2] from address+4. R[t] = if BigEndian() then value<63:32> else value<31:0>; R[t2] = if BigEndian() then value<31:0> else value<63:32>;
Operational information
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.