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MOV, MOVS (register)

Move (register) copies a value from a register to the destination register.

If the destination register is not the PC, the MOVS variant of the instruction updates the condition flags based on the result.

The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. If the destination register is the PC:

  • The MOV variant of the instruction is a branch. In the T32 instruction set (encoding T1) this is a simple branch, and in the A32 instruction set it is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC.
  • The MOVS variant of the instruction performs an exception return without the use of the stack. In this case:
    • The PE branches to the address written to the PC, and restores PSTATE from SPSR_<current_mode>.
    • The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from AArch32 state.
    • The instruction is undefined in Hyp mode.
    • The instruction is constrained unpredictable in User mode and System mode.

This instruction is used by the aliases ASRS (immediate), ASR (immediate), LSLS (immediate), LSL (immediate), LSRS (immediate), LSR (immediate), RORS (immediate), ROR (immediate), RRXS, and RRX.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 , T2 and T3 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 11110001101S(0)(0)(0)(0)Rdimm5type0Rm
cond

MOV, rotate right with extend (S == 0 && imm5 == 00000 && type == 11)

MOV{<c>}{<q>} <Rd>, <Rm>, RRX

MOV, shift or rotate by value (S == 0 && !(imm5 == 00000 && type == 11))

MOV{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount>}

MOVS, rotate right with extend (S == 1 && imm5 == 00000 && type == 11)

MOVS{<c>}{<q>} <Rd>, <Rm>, RRX

MOVS, shift or rotate by value (S == 1 && !(imm5 == 00000 && type == 11))

MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount>}

d = UInt(Rd);  m = UInt(Rm);  setflags = (S == '1');
(shift_t, shift_n) = DecodeImmShift(type, imm5);

T1

1514131211109876543210
01000110DRmRd

T1

MOV{<c>}{<q>} <Rd>, <Rm>

d = UInt(D:Rd);  m = UInt(Rm);  setflags = FALSE;
(shift_t, shift_n) = (SRType_LSL, 0);
if d == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE;

T2

1514131211109876543210
000!= 11imm5RmRd
op

T2

MOV<c>{<q>} <Rd>, <Rm> {, <shift> #<amount>} // (Inside IT block)

MOVS{<q>} <Rd>, <Rm> {, <shift> #<amount>} // (Outside IT block)

d = UInt(Rd);  m = UInt(Rm);  setflags = !InITBlock();
(shift_t, shift_n) = DecodeImmShift(op, imm5);
if op == '00' && imm5 == '00000' && InITBlock() then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If op == '00' && imm5 == '00000' && InITBlock(), then one of the following behaviors must occur:

  • The instruction is undefined.
  • The instruction executes as if it passed its condition code check.
  • The instruction executes as NOP, as if it failed its condition code check.
  • The instruction executes as MOV Rd, Rm.

T3

15141312111098765432101514131211109876543210
11101010010S1111(0)imm3Rdimm2typeRm

MOV, rotate right with extend (S == 0 && imm3 == 000 && imm2 == 00 && type == 11)

MOV{<c>}{<q>} <Rd>, <Rm>, RRX

MOV, shift or rotate by value (S == 0 && !(imm3 == 000 && imm2 == 00 && type == 11))

MOV{<c>}.W <Rd>, <Rm> {, LSL #0} // (<Rd>, <Rm> can be represented in T1)

MOV<c>.W <Rd>, <Rm> {, <shift> #<amount>} // (Inside IT block, and <Rd>, <Rm>, <shift>, <amount> can be represented in T2)

MOV{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount>}

MOVS, rotate right with extend (S == 1 && imm3 == 000 && imm2 == 00 && type == 11)

MOVS{<c>}{<q>} <Rd>, <Rm>, RRX

MOVS, shift or rotate by value (S == 1 && !(imm3 == 000 && imm2 == 00 && type == 11))

MOVS.W <Rd>, <Rm> {, <shift> #<amount>} // (Outside IT block, and <Rd>, <Rm>, <shift>, <amount> can be represented in T1 or T2)

MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount>}

d = UInt(Rd);  m = UInt(Rm);  setflags = (S == '1');
(shift_t, shift_n) = DecodeImmShift(type, imm3:imm2);
if d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rd>

For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If the PC is used:

  • For the MOV variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC. Arm deprecates use of the instruction if <Rn> is the PC.
  • For the MOVS variant, the instruction performs an exception return, that restores PSTATE from SPSR_<current_mode>. Arm deprecates use of the instruction if <Rn> is not the LR, or if the optional shift or RRX argument is specified.

For encoding T1: is the general-purpose destination register, encoded in the "D:Rd" field. If the PC is used:

For encoding T2 and T3: is the general-purpose destination register, encoded in the "Rd" field.

<Rm>

For encoding A1 and T1: is the general-purpose source register, encoded in the "Rm" field. The PC can be used. Arm deprecates use of the instruction if <Rd> is the PC.

For encoding T2 and T3: is the general-purpose source register, encoded in the "Rm" field.

<shift> For encoding A1 and T3: is the type of shift to be applied to the source register, encoded in type:
type <shift>
00 LSL
01 LSR
10 ASR
11 ROR
For encoding T2: is the type of shift to be applied to the source register, encoded in op:
op <shift>
00 LSL
01 LSR
10 ASR
<amount>

For encoding A1: is the shift amount, in the range 0 to 31 (when <shift> = LSL), or 1 to 31 (when <shift> = ROR) or 1 to 32 (when <shift> = LSR or ASR), encoded in the "imm5" field as <amount> modulo 32.

For encoding T2: is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR), encoded in the "imm5" field as <amount> modulo 32.

For encoding T3: is the shift amount, in the range 0 to 31 (when <shift> = LSL) or 1 to 31 (when <shift> = ROR), or 1 to 32 (when <shift> = LSR or ASR), encoded in the "imm3:imm2" field as <amount> modulo 32.

Alias Conditions

AliasOf variantIs preferred when
ASRS (immediate)T3 (MOVS, shift or rotate by value), A1 (MOVS, shift or rotate by value)S == '1' && type == '10'
ASRS (immediate)T2op == '10' && !InITBlock()
ASR (immediate)T3 (MOV, shift or rotate by value), A1 (MOV, shift or rotate by value)S == '0' && type == '10'
ASR (immediate)T2op == '10' && InITBlock()
LSLS (immediate)T3 (MOVS, shift or rotate by value)S == '1' && imm3:Rd:imm2 != '000xxxx00' && type == '00'
LSLS (immediate)A1 (MOVS, shift or rotate by value)S == '1' && imm5 != '00000' && type == '00'
LSLS (immediate)T2op == '00' && imm5 != '00000' && !InITBlock()
LSL (immediate)T3 (MOV, shift or rotate by value)S == '0' && imm3:Rd:imm2 != '000xxxx00' && type == '00'
LSL (immediate)A1 (MOV, shift or rotate by value)S == '0' && imm5 != '00000' && type == '00'
LSL (immediate)T2op == '00' && imm5 != '00000' && InITBlock()
LSRS (immediate)T3 (MOVS, shift or rotate by value), A1 (MOVS, shift or rotate by value)S == '1' && type == '01'
LSRS (immediate)T2op == '01' && !InITBlock()
LSR (immediate)T3 (MOV, shift or rotate by value), A1 (MOV, shift or rotate by value)S == '0' && type == '01'
LSR (immediate)T2op == '01' && InITBlock()
RORS (immediate)T3 (MOVS, shift or rotate by value)S == '1' && imm3:Rd:imm2 != '000xxxx00' && type == '11'
RORS (immediate)A1 (MOVS, shift or rotate by value)S == '1' && imm5 != '00000' && type == '11'
ROR (immediate)T3 (MOV, shift or rotate by value)S == '0' && imm3:Rd:imm2 != '000xxxx00' && type == '11'
ROR (immediate)A1 (MOV, shift or rotate by value)S == '0' && imm5 != '00000' && type == '11'
RRXST3 (MOVS, rotate right with extend)S == '1' && imm3 == '000' && imm2 == '00' && type == '11'
RRXSA1 (MOVS, rotate right with extend)S == '1' && imm5 == '00000' && type == '11'
RRXT3 (MOV, rotate right with extend)S == '0' && imm3 == '000' && imm2 == '00' && type == '11'
RRXA1 (MOV, rotate right with extend)S == '0' && imm5 == '00000' && type == '11'

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    (shifted, carry) = Shift_C(R[m], shift_t, shift_n, PSTATE.C);
    result = shifted;
    if d == 15 then
        if setflags then
            ALUExceptionReturn(result);
        else
            ALUWritePC(result);
    else
        R[d] = result;
        if setflags then
            PSTATE.N = result<31>;
            PSTATE.Z = IsZeroBit(result);
            PSTATE.C = carry;
            // PSTATE.V unchanged

Operational information

If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:

  • The execution time of this instruction is independent of:
    • The values of the data supplied in any of its registers.
    • The values of the NZCV flags.
  • The response of this instruction to asynchronous exceptions does not vary based on:
    • The values of the data supplied in any of its registers.
    • The values of the NZCV flags.
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