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MOV, MOVS (register-shifted register)

Move (register-shifted register) copies a register-shifted register value to the destination register. It can optionally update the condition flags based on the value.

This instruction is used by the aliases ASRS (register), ASR (register), LSLS (register), LSL (register), LSRS (register), LSR (register), RORS (register), and ROR (register).

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 11110001101S(0)(0)(0)(0)RdRs0type1Rm
cond

Flag setting (S == 1)

MOVS{<c>}{<q>} <Rd>, <Rm>, <type> <Rs>

Not flag setting (S == 0)

MOV{<c>}{<q>} <Rd>, <Rm>, <type> <Rs>

d = UInt(Rd);  m = UInt(Rm);  s = UInt(Rs);
setflags = (S == '1');  shift_t = DecodeRegShift(type);
if d == 15 || m == 15 || s == 15 then UNPREDICTABLE;

T1

1514131211109876543210
0100000xxxRsRdm
op

Arithmetic shift right (op == 0100)

MOV<c>{<q>} <Rdm>, <Rdm>, ASR <Rs> // (Inside IT block)

MOVS{<q>} <Rdm>, <Rdm>, ASR <Rs> // (Outside IT block)

Logical shift left (op == 0010)

MOV<c>{<q>} <Rdm>, <Rdm>, LSL <Rs> // (Inside IT block)

MOVS{<q>} <Rdm>, <Rdm>, LSL <Rs> // (Outside IT block)

Logical shift right (op == 0011)

MOV<c>{<q>} <Rdm>, <Rdm>, LSR <Rs> // (Inside IT block)

MOVS{<q>} <Rdm>, <Rdm>, LSR <Rs> // (Outside IT block)

Rotate right (op == 0111)

MOV<c>{<q>} <Rdm>, <Rdm>, ROR <Rs> // (Inside IT block)

MOVS{<q>} <Rdm>, <Rdm>, ROR <Rs> // (Outside IT block)

if !(op IN {'0010', '0011', '0100', '0111'}) then SEE "Related encodings";
d = UInt(Rdm);  m = UInt(Rdm);  s = UInt(Rs);
setflags = !InITBlock();  shift_t = DecodeRegShift(op<2>:op<0>);

T2

15141312111098765432101514131211109876543210
111110100typeSRm1111Rd0000Rs

Flag setting (S == 1)

MOVS.W <Rd>, <Rm>, <type> <Rs> // (Outside IT block, and <Rd>, <Rm>, <type>, <Rs> can be represented in T1)

MOVS{<c>}{<q>} <Rd>, <Rm>, <type> <Rs>

Not flag setting (S == 0)

MOV<c>.W <Rd>, <Rm>, <type> <Rs> // (Inside IT block, and <Rd>, <Rm>, <type>, <Rs> can be represented in T1)

MOV{<c>}{<q>} <Rd>, <Rm>, <type> <Rs>

d = UInt(Rd);  m = UInt(Rm);  s = UInt(Rs);
setflags = (S == '1');  shift_t = DecodeRegShift(type);
if d == 15 || m == 15 || s == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13

Related encodings: In encoding T1, for an op field value that is not described above, see Data-processing (two low registers).

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rdm>

Is the general-purpose source register and the destination register, encoded in the "Rdm" field.

<Rd>

Is the general-purpose destination register, encoded in the "Rd" field.

<Rm>

Is the general-purpose source register, encoded in the "Rm" field.

<type> Is the type of shift to be applied to the second source register, encoded in type:
type <type>
00 LSL
01 LSR
10 ASR
11 ROR
<Rs>

Is the general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.

Alias Conditions

AliasOf variantIs preferred when
ASRS (register)A1 (flag setting)S == '1' && type == '10'
ASRS (register)T1 (arithmetic shift right)op == '0100' && !InITBlock()
ASRS (register)T2 (flag setting)type == '10' && S == '1'
ASR (register)A1 (not flag setting)S == '0' && type == '10'
ASR (register)T1 (arithmetic shift right)op == '0100' && InITBlock()
ASR (register)T2 (not flag setting)type == '10' && S == '0'
LSLS (register)A1 (flag setting)S == '1' && type == '00'
LSLS (register)T1 (logical shift left)op == '0010' && !InITBlock()
LSLS (register)T2 (flag setting)type == '00' && S == '1'
LSL (register)A1 (not flag setting)S == '0' && type == '00'
LSL (register)T1 (logical shift left)op == '0010' && InITBlock()
LSL (register)T2 (not flag setting)type == '00' && S == '0'
LSRS (register)A1 (flag setting)S == '1' && type == '01'
LSRS (register)T1 (logical shift right)op == '0011' && !InITBlock()
LSRS (register)T2 (flag setting)type == '01' && S == '1'
LSR (register)A1 (not flag setting)S == '0' && type == '01'
LSR (register)T1 (logical shift right)op == '0011' && InITBlock()
LSR (register)T2 (not flag setting)type == '01' && S == '0'
RORS (register)A1 (flag setting)S == '1' && type == '11'
RORS (register)T1 (rotate right)op == '0111' && !InITBlock()
RORS (register)T2 (flag setting)type == '11' && S == '1'
ROR (register)A1 (not flag setting)S == '0' && type == '11'
ROR (register)T1 (rotate right)op == '0111' && InITBlock()
ROR (register)T2 (not flag setting)type == '11' && S == '0'

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    shift_n = UInt(R[s]<7:0>);
    (result, carry) = Shift_C(R[m], shift_t, shift_n, PSTATE.C);
    R[d] = result;
    if setflags then
        PSTATE.N = result<31>;
        PSTATE.Z = IsZeroBit(result);
        PSTATE.C = carry;
        // PSTATE.V unchanged

Operational information

If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:

  • The execution time of this instruction is independent of:
    • The values of the data supplied in any of its registers.
    • The values of the NZCV flags.
  • The response of this instruction to asynchronous exceptions does not vary based on:
    • The values of the data supplied in any of its registers.
    • The values of the NZCV flags.
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