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ORN, ORNS (register)

Bitwise OR NOT (register) performs a bitwise (inclusive) OR of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result.

T1

15141312111098765432101514131211109876543210
11101010011S!= 1111(0)imm3Rdimm2typeRm
Rn

ORN, rotate right with extend (S == 0 && imm3 == 000 && imm2 == 00 && type == 11)

ORN{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX

ORN, shift or rotate by value (S == 0 && !(imm3 == 000 && imm2 == 00 && type == 11))

ORN{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>}

ORNS, rotate right with extend (S == 1 && imm3 == 000 && imm2 == 00 && type == 11)

ORNS{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX

ORNS, shift or rotate by value (S == 1 && !(imm3 == 000 && imm2 == 00 && type == 11))

ORNS{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>}

if Rn == '1111' then SEE "MVN (register)";
d = UInt(Rd);  n = UInt(Rn);  m = UInt(Rm);  setflags = (S == '1');
(shift_t, shift_n) = DecodeImmShift(type, imm3:imm2);
if d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rd>

Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>

Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>

Is the second general-purpose source register, encoded in the "Rm" field.

<shift> Is the type of shift to be applied to the second source register, encoded in type:
type <shift>
00 LSL
01 LSR
10 ASR
11 ROR
<amount>

Is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR), encoded in the "imm3:imm2" field as <amount> modulo 32.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    (shifted, carry) = Shift_C(R[m], shift_t, shift_n, PSTATE.C);
    result = R[n] OR NOT(shifted);
    R[d] = result;
    if setflags then
        PSTATE.N = result<31>;
        PSTATE.Z = IsZeroBit(result);
        PSTATE.C = carry;
        // PSTATE.V unchanged

Operational information

If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:

  • The execution time of this instruction is independent of:
    • The values of the data supplied in any of its registers.
    • The values of the NZCV flags.
  • The response of this instruction to asynchronous exceptions does not vary based on:
    • The values of the data supplied in any of its registers.
    • The values of the NZCV flags.
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