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PLD, PLDW (register)

Preload Data (register) signals the memory system that data memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as preloading the cache line containing the specified address into the data cache.

The PLD instruction signals that the likely memory access is a read, and the PLDW instruction signals that it is a write.

The effect of a PLD or PLDW instruction is implementation defined. For more information, see Preloading caches.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
11110111UR01Rn(1)(1)(1)(1)imm5type0Rm

Preload read, optional shift or rotate (R == 1 && !(imm5 == 00000 && type == 11))

PLD{<c>}{<q>} [<Rn>, {+/-}<Rm> {, <shift> #<amount>}]

Preload read, rotate right with extend (R == 1 && imm5 == 00000 && type == 11)

PLD{<c>}{<q>} [<Rn>, {+/-}<Rm> , RRX]

Preload write, optional shift or rotate (R == 0 && !(imm5 == 00000 && type == 11))

PLDW{<c>}{<q>} [<Rn>, {+/-}<Rm> {, <shift> #<amount>}]

Preload write, rotate right with extend (R == 0 && imm5 == 00000 && type == 11)

PLDW{<c>}{<q>} [<Rn>, {+/-}<Rm> , RRX]

n = UInt(Rn);  m = UInt(Rm);  add = (U == '1');  is_pldw = (R == '0');
(shift_t, shift_n) = DecodeImmShift(type, imm5);
if m == 15 || (n == 15 && is_pldw) then UNPREDICTABLE;

T1

15141312111098765432101514131211109876543210
1111100000W1!= 11111111000000imm2Rm
Rn

Preload read (W == 0)

PLD{<c>}{<q>} [<Rn>, {+}<Rm> {, LSL #<amount>}]

Preload write (W == 1)

PLDW{<c>}{<q>} [<Rn>, {+}<Rm> {, LSL #<amount>}]

if Rn == '1111' then SEE "PLD (literal)";
n = UInt(Rn);  m = UInt(Rm);  add = TRUE;  is_pldw = (W == '1');
(shift_t, shift_n) = (SRType_LSL, UInt(imm2));
if m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

For encoding A1: see Standard assembler syntax fields. <c> must be AL or omitted.

For encoding T1: see Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rn>

For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The PC can be used.

For encoding T1: is the general-purpose base register, encoded in the "Rn" field.

+/- Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:
U +/-
0 -
1 +
+

Specifies the index register is added to the base register.

<Rm>

Is the general-purpose index register, encoded in the "Rm" field.

<shift> Is the type of shift to be applied to the index register, encoded in type:
type <shift>
00 LSL
01 LSR
10 ASR
11 ROR
<amount>

For encoding A1: is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR) encoded in the "imm5" field as <amount> modulo 32.

For encoding T1: is the shift amount, in the range 0 to 3, defaulting to 0 and encoded in the "imm2" field.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    offset = Shift(R[m], shift_t, shift_n, PSTATE.C);
    address = if add then (R[n] + offset) else (R[n] - offset);
    if is_pldw then
        Hint_PreloadDataForWrite(address);
    else
        Hint_PreloadData(address);
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