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RSC, RSCS (register)

Reverse Subtract with Carry (register) subtracts a register value and the value of NOT (Carry flag) from an optionally-shifted register value, and writes the result to the destination register.

If the destination register is not the PC, the RSCS variant of the instruction updates the condition flags based on the result.

The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. ARM deprecates any use of these encodings. However, when the destination register is the PC:

A1

313029282726252423222120191817161514131211109876543210
!= 11110000111SRnRdimm5type0Rm
cond

RSC, rotate right with extend (S == 0 && imm5 == 00000 && type == 11)

RSC{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX

RSC, shift or rotate by value (S == 0 && !(imm5 == 00000 && type == 11))

RSC{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>}

RSCS, rotate right with extend (S == 1 && imm5 == 00000 && type == 11)

RSCS{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX

RSCS, shift or rotate by value (S == 1 && !(imm5 == 00000 && type == 11))

RSCS{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>}

d = UInt(Rd);  n = UInt(Rn);  m = UInt(Rm);  setflags = (S == '1');
(shift_t, shift_n) = DecodeImmShift(type, imm5);

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rd>

Is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <Rn>. Arm deprecates using the PC as the destination register, but if the PC is used:

<Rn>

Is the first general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.

<Rm>

Is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.

<shift> Is the type of shift to be applied to the second source register, encoded in type:
type <shift>
00 LSL
01 LSR
10 ASR
11 ROR
<amount>

Is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR) encoded in the "imm5" field as <amount> modulo 32.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    shifted = Shift(R[m], shift_t, shift_n, PSTATE.C);
    (result, nzcv) = AddWithCarry(NOT(R[n]), shifted, PSTATE.C);
    if d == 15 then
        if setflags then
            ALUExceptionReturn(result);
        else
            ALUWritePC(result);
    else
        R[d] = result;
        if setflags then
            PSTATE.<N,Z,C,V> = nzcv;

Operational information

If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:

  • The execution time of this instruction is independent of:
    • The values of the data supplied in any of its registers.
    • The values of the NZCV flags.
  • The response of this instruction to asynchronous exceptions does not vary based on:
    • The values of the data supplied in any of its registers.
    • The values of the NZCV flags.
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