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Data-processing and miscellaneous instructions

These instructions are under the top-level.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 00 op0 op1 op2 op3 op4

Extra load/store

These instructions are under Data-processing and miscellaneous instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 000 op0 1 != 00 1

Load/Store Dual, Half, Signed Byte (register)

These instructions are under Extra load/store.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 P U 0 W o1 Rn Rt (0) (0) (0) (0) 1 != 00 1 Rm
cond op2

The following constraints also apply to this encoding: cond != 1111 && op2 != 00 && cond != 1111 && op2 != 00

Decode fields Instruction Details
P W o1 op2
0 0 0 01 STRH (register)post-indexed
0 0 0 10 LDRD (register)post-indexed
0 0 0 11 STRD (register)post-indexed
0 0 1 01 LDRH (register)post-indexed
0 0 1 10 LDRSB (register)post-indexed
0 0 1 11 LDRSH (register)post-indexed
0 1 0 01 STRHT
0 1 0 10 UNALLOCATED
0 1 0 11 UNALLOCATED
0 1 1 01 LDRHT
0 1 1 10 LDRSBT
0 1 1 11 LDRSHT
1 0 01 STRH (register)pre-indexed
1 0 10 LDRD (register)pre-indexed
1 0 11 STRD (register)pre-indexed
1 1 01 LDRH (register)pre-indexed
1 1 10 LDRSB (register)pre-indexed
1 1 11 LDRSH (register)pre-indexed

Load/Store Dual, Half, Signed Byte (immediate, literal)

These instructions are under Extra load/store.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 P U 1 W o1 Rn Rt imm4H 1 != 00 1 imm4L
cond op2

The following constraints also apply to this encoding: cond != 1111 && op2 != 00 && cond != 1111 && op2 != 00

Decode fields Instruction Details
P:W o1 Rn op2
0 1111 10 LDRD (literal)
!= 01 1 1111 01 LDRH (literal)
!= 01 1 1111 10 LDRSB (literal)
!= 01 1 1111 11 LDRSH (literal)
00 0 != 1111 10 LDRD (immediate)post-indexed
00 0 01 STRH (immediate)post-indexed
00 0 11 STRD (immediate)post-indexed
00 1 != 1111 01 LDRH (immediate)post-indexed
00 1 != 1111 10 LDRSB (immediate)post-indexed
00 1 != 1111 11 LDRSH (immediate)post-indexed
01 0 != 1111 10 UNALLOCATED
01 0 01 STRHT
01 0 11 UNALLOCATED
01 1 01 LDRHT
01 1 10 LDRSBT
01 1 11 LDRSHT
10 0 != 1111 10 LDRD (immediate)offset
10 0 01 STRH (immediate)offset
10 0 11 STRD (immediate)offset
10 1 != 1111 01 LDRH (immediate)offset
10 1 != 1111 10 LDRSB (immediate)offset
10 1 != 1111 11 LDRSH (immediate)offset
11 0 != 1111 10 LDRD (immediate)pre-indexed
11 0 01 STRH (immediate)pre-indexed
11 0 11 STRD (immediate)pre-indexed
11 1 != 1111 01 LDRH (immediate)pre-indexed
11 1 != 1111 10 LDRSB (immediate)pre-indexed
11 1 != 1111 11 LDRSH (immediate)pre-indexed

Multiply and Accumulate

These instructions are under Data-processing and miscellaneous instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 0 opc S RdHi RdLo Rm 1 0 0 1 Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc S
000 MUL, MULS
001 MLA, MLAS
010 0 UMAAL
010 1 UNALLOCATED
011 0 MLS
011 1 UNALLOCATED
100 UMULL, UMULLS
101 UMLAL, UMLALS
110 SMULL, SMULLS
111 SMLAL, SMLALS

Synchronization primitives and Load-Acquire/Store-Release

These instructions are under Data-processing and miscellaneous instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0001 op0 11 1001
Decode fields Instruction details
op0
0 UNALLOCATED
1 Load/Store Exclusive and Load-Acquire/Store-Release

Load/Store Exclusive and Load-Acquire/Store-Release

These instructions are under Synchronization primitives and Load-Acquire/Store-Release.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 1 1 type L Rn xRd (1) (1) ex ord 1 0 0 1 xRt
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
type L ex ord
00 0 0 0 STL
00 0 0 1 UNALLOCATED
00 0 1 0 STLEX
00 0 1 1 STREX
00 1 0 0 LDA
00 1 0 1 UNALLOCATED
00 1 1 0 LDAEX
00 1 1 1 LDREX
01 0 0 UNALLOCATED
01 0 1 0 STLEXD
01 0 1 1 STREXD
01 1 0 UNALLOCATED
01 1 1 0 LDAEXD
01 1 1 1 LDREXD
10 0 0 0 STLB
10 0 0 1 UNALLOCATED
10 0 1 0 STLEXB
10 0 1 1 STREXB
10 1 0 0 LDAB
10 1 0 1 UNALLOCATED
10 1 1 0 LDAEXB
10 1 1 1 LDREXB
11 0 0 0 STLH
11 0 0 1 UNALLOCATED
11 0 1 0 STLEXH
11 0 1 1 STREXH
11 1 0 0 LDAH
11 1 0 1 UNALLOCATED
11 1 1 0 LDAEXH
11 1 1 1 LDREXH

Miscellaneous

These instructions are under Data-processing and miscellaneous instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 00010 op0 0 0 op1
Decode fields Instruction details
op0 op1
00 001 UNALLOCATED
00 010 UNALLOCATED
00 011 UNALLOCATED
00 110 UNALLOCATED
01 001 BX
01 010 BXJ
01 011 BLX (register)
01 110 UNALLOCATED
10 001 UNALLOCATED
10 010 UNALLOCATED
10 011 UNALLOCATED
10 110 UNALLOCATED
11 001 CLZ
11 010 UNALLOCATED
11 011 UNALLOCATED
11 110 ERET
111 Exception Generation
000 Move special register (register)
100 Cyclic Redundancy Check
101 Integer Saturating Arithmetic

Exception Generation

These instructions are under Miscellaneous.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 1 0 opc 0 imm12 0 1 1 1 imm4
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
00 HLT
01 BKPT
10 HVC
11 SMC

Move special register (register)

These instructions are under Miscellaneous.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 1 0 opc 0 mask Rd (0) (0) B m 0 0 0 0 Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc B
x0 0 MRS
x0 1 MRS (Banked register)
x1 0 MSR (register)
x1 1 MSR (Banked register)

Cyclic Redundancy Check

These instructions are under Miscellaneous.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 1 0 sz 0 Rn Rd (0) (0) C (0) 0 1 0 0 Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
sz C
00 0 CRC32CRC32B
00 1 CRC32CCRC32CB
01 0 CRC32CRC32H
01 1 CRC32CCRC32CH
10 0 CRC32CRC32W
10 1 CRC32CCRC32CW
11 CONSTRAINED UNPREDICTABLE

The behavior of the CONSTRAINED UNPREDICTABLE encodings in this table is described in CONSTRAINED UNPREDICTABLE behavior for A32 and T32 instruction encodings


Integer Saturating Arithmetic

These instructions are under Miscellaneous.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 1 0 opc 0 Rn Rd (0) (0) (0) (0) 0 1 0 1 Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
00 QADD
01 QSUB
10 QDADD
11 QDSUB

Halfword Multiply and Accumulate

These instructions are under Data-processing and miscellaneous instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 1 0 opc 0 Rd Ra Rm 1 M N 0 Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111


Data-processing register (immediate shift)

These instructions are under Data-processing and miscellaneous instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 000 op0 op1 0

The following constraints also apply to this encoding: op0:op1 != 100


Integer Data Processing (three register, immediate shift)

These instructions are under Data-processing register (immediate shift).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 0 opc S Rn Rd imm5 type 0 Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111


Integer Test and Compare (two register, immediate shift)

These instructions are under Data-processing register (immediate shift).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 1 0 opc 1 Rn (0) (0) (0) (0) imm5 type 0 Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
00 TST (register)
01 TEQ (register)
10 CMP (register)
11 CMN (register)

Logical Arithmetic (three register, immediate shift)

These instructions are under Data-processing register (immediate shift).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 1 1 opc S Rn Rd imm5 type 0 Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
00 ORR, ORRS (register)
01 MOV, MOVS (register)
10 BIC, BICS (register)
11 MVN, MVNS (register)

Data-processing register (register shift)

These instructions are under Data-processing and miscellaneous instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 000 op0 op1 0 1

The following constraints also apply to this encoding: op0:op1 != 100


Integer Data Processing (three register, register shift)

These instructions are under Data-processing register (register shift).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 0 opc S Rn Rd Rs 0 type 1 Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111


Integer Test and Compare (two register, register shift)

These instructions are under Data-processing register (register shift).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 1 0 opc 1 Rn (0) (0) (0) (0) Rs 0 type 1 Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111


Logical Arithmetic (three register, register shift)

These instructions are under Data-processing register (register shift).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 1 1 opc S Rn Rd Rs 0 type 1 Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111


Data-processing immediate

These instructions are under Data-processing and miscellaneous instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 001 op0 op1

Integer Data Processing (two register and immediate)

These instructions are under Data-processing immediate.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 1 0 opc S Rn Rd imm12
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc S Rn
000 AND, ANDS (immediate)
001 EOR, EORS (immediate)
010 0 != 11x1 SUB, SUBS (immediate)SUB
010 0 1101 SUB, SUBS (SP minus immediate)SUB
010 0 1111 ADRA2
010 1 != 1101 SUB, SUBS (immediate)SUBS
010 1 1101 SUB, SUBS (SP minus immediate)SUBS
011 RSB, RSBS (immediate)
100 0 != 11x1 ADD, ADDS (immediate)ADD
100 0 1101 ADD, ADDS (SP plus immediate)ADD
100 0 1111 ADRA1
100 1 != 1101 ADD, ADDS (immediate)ADDS
100 1 1101 ADD, ADDS (SP plus immediate)ADDS
101 ADC, ADCS (immediate)
110 SBC, SBCS (immediate)
111 RSC, RSCS (immediate)

Move Halfword (immediate)

These instructions are under Data-processing immediate.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 1 1 0 H 0 0 imm4 Rd imm12
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
H
0 MOV, MOVS (immediate)
1 MOVT

Move Special Register and Hints (immediate)

These instructions are under Data-processing immediate.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 1 1 0 R 1 0 imm4 (1) (1) (1) (1) imm12
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details Architecture Version
R:imm4 imm12
!= 00000 MSR (immediate) -
00000 xxxx00000000 NOP -
00000 xxxx00000001 YIELD -
00000 xxxx00000010 WFE -
00000 xxxx00000011 WFI -
00000 xxxx00000100 SEV -
00000 xxxx00000101 SEVL -
00000 xxxx0000011x Reserved hint, behaves as NOP -
00000 xxxx00001xxx Reserved hint, behaves as NOP -
00000 xxxx00010000 ESB Armv8.2
00000 xxxx00010001 Reserved hint, behaves as NOP -
00000 xxxx00010010 TSB CSYNC Armv8.4
00000 xxxx00010011 Reserved hint, behaves as NOP -
00000 xxxx00010100 CSDB -
00000 xxxx00010101 Reserved hint, behaves as NOP -
00000 xxxx00011xxx Reserved hint, behaves as NOP -
00000 xxxx0001111x Reserved hint, behaves as NOP -
00000 xxxx001xxxxx Reserved hint, behaves as NOP -
00000 xxxx01xxxxxx Reserved hint, behaves as NOP -
00000 xxxx10xxxxxx Reserved hint, behaves as NOP -
00000 xxxx110xxxxx Reserved hint, behaves as NOP -
00000 xxxx1110xxxx Reserved hint, behaves as NOP -
00000 xxxx1111xxxx DBG -

Integer Test and Compare (one register and immediate)

These instructions are under Data-processing immediate.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 1 1 0 opc 1 Rn (0) (0) (0) (0) imm12
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
00 TST (immediate)
01 TEQ (immediate)
10 CMP (immediate)
11 CMN (immediate)

Logical Arithmetic (two register and immediate)

These instructions are under Data-processing immediate.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 1 1 1 opc S Rn Rd imm12
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111