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System register access, Advanced SIMD, floating-point, and Supervisor call

These instructions are under the top-level.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 11 op0 op1 op2

System register load/store and 64-bit move

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
110 op0 111
Decode fields Instruction details
op0
00x0 System register 64-bit move
!= 00x0 System register load/store

System register 64-bit move

These instructions are under System register load/store and 64-bit move.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 1 1 0 0 0 D 0 L Rt2 Rt 1 1 1 cp15 opc1 CRm
Decode fields Instruction Details
cond D L
!= 1111 1 0 MCRR
!= 1111 1 1 MRRC
0 UNALLOCATED
1111 1 UNALLOCATED

System register load/store

These instructions are under System register load/store and 64-bit move.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 1 1 0 P U D W L Rn CRd 1 1 1 cp15 imm8

The following constraints also apply to this encoding: P:U:D:W != 00x0

Decode fields Instruction Details
cond P:U:W D L Rn CRd cp15
!= 1111 != 000 0 != 0101 0 UNALLOCATED
!= 1111 != 000 0 1 1111 0101 0 LDC (literal)
!= 1111 != 000 1 UNALLOCATED
!= 1111 != 000 1 0101 0 UNALLOCATED
!= 1111 0x1 0 0 0101 0 STCpost-indexed
!= 1111 0x1 0 1 != 1111 0101 0 LDC (immediate)post-indexed
!= 1111 010 0 0 0101 0 STCunindexed
!= 1111 010 0 1 != 1111 0101 0 LDC (immediate)unindexed
!= 1111 1x0 0 0 0101 0 STCoffset
!= 1111 1x0 0 1 != 1111 0101 0 LDC (immediate)offset
!= 1111 1x1 0 0 0101 0 STCpre-indexed
!= 1111 1x1 0 1 != 1111 0101 0 LDC (immediate)pre-indexed
1111 != 000 UNALLOCATED

Floating-point data-processing

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cond 1110 op0 op1 10 op2 op3 0
Decode fields Instruction details
cond op0 op1 op2 op3
1111 0xxx != 00 0 Floating-point conditional select
1111 1x00 != 00 Floating-point minNum/maxNum
1111 1x11 0000 != 00 1 Floating-point extraction and insertion
1111 1x11 1xxx != 00 1 Floating-point directed convert to integer
!= 1111 1x11 1 Floating-point data-processing (two registers)
!= 1111 1x11 0 Floating-point move immediate
!= 1111 != 1x11 Floating-point data-processing (three registers)

Floating-point conditional select

These instructions are under Floating-point data-processing.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 0 0 D cc Vn Vd 1 0 != 00 N 0 M 0 Vm
size

The following constraints also apply to this encoding: size != 00 && size != 00


Floating-point minNum/maxNum

These instructions are under Floating-point data-processing.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 0 1 D 0 0 Vn Vd 1 0 != 00 N op M 0 Vm
size

The following constraints also apply to this encoding: size != 00 && size != 00

Decode fields Instruction Details
size op
0 VMAXNM
01 UNALLOCATED
1 VMINNM

Floating-point extraction and insertion

These instructions are under Floating-point data-processing.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 0 1 D 1 1 0 0 0 0 Vd 1 0 != 00 op 1 M 0 Vm
size

The following constraints also apply to this encoding: size != 00 && size != 00

Decode fields Instruction Details Architecture Version
size op
01 UNALLOCATED -
10 0 VMOVX Armv8.2
10 1 VINS Armv8.2
11 UNALLOCATED -

Floating-point directed convert to integer

These instructions are under Floating-point data-processing.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 0 1 D 1 1 1 o1 RM Vd 1 0 != 00 op 1 M 0 Vm
size

The following constraints also apply to this encoding: size != 00 && size != 00


Floating-point data-processing (two registers)

These instructions are under Floating-point data-processing.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 1 1 1 0 1 D 1 1 o1 opc2 Vd 1 0 size o3 1 M 0 Vm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details Architecture Version
o1 opc2 size o3
00 UNALLOCATED -
0 000 01 0 UNALLOCATED -
0 000 1 VABS -
0 000 10 0 VMOV (register)single-precision scalar -
0 000 11 0 VMOV (register)double-precision scalar -
0 001 0 VNEG -
0 001 1 VSQRT -
0 01x 01 UNALLOCATED -
0 010 0 VCVTBhalf-precision to double-precision -
0 010 1 VCVTThalf-precision to double-precision -
0 011 0 VCVTBdouble-precision to half-precision -
0 011 1 VCVTTdouble-precision to half-precision -
0 100 0 VCMPA1 -
0 100 1 VCMPEA1 -
0 101 0 VCMPA2 -
0 101 1 VCMPEA2 -
0 110 0 VRINTR -
0 110 1 VRINTZ (floating-point) -
0 111 0 VRINTX (floating-point) -
0 111 01 1 UNALLOCATED -
0 111 10 1 VCVT (between double-precision and single-precision)single-precision to double-precision -
0 111 11 1 VCVT (between double-precision and single-precision)double-precision to single-precision -
1 000 VCVT (integer to floating-point, floating-point) -
1 001 01 UNALLOCATED -
1 001 10 UNALLOCATED -
1 001 11 0 UNALLOCATED -
1 001 11 1 VJCVT Armv8.3
1 01x VCVT (between floating-point and fixed-point, floating-point) -
1 100 0 VCVTR -
1 100 1 VCVT (floating-point to integer, floating-point) -
1 101 0 VCVTR -
1 101 1 VCVT (floating-point to integer, floating-point) -
1 11x VCVT (between floating-point and fixed-point, floating-point) -

Floating-point move immediate

These instructions are under Floating-point data-processing.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 1 1 1 0 1 D 1 1 imm4H Vd 1 0 size (0) 0 (0) 0 imm4L
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details Architecture Version
size
00 UNALLOCATED -
01 VMOV (immediate)half-precision scalar Armv8.2
10 VMOV (immediate)single-precision scalar -
11 VMOV (immediate)double-precision scalar -

Floating-point data-processing (three registers)

These instructions are under Floating-point data-processing.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 1 1 1 0 o0 D o1 Vn Vd 1 0 size N o2 M 0 Vm
cond

The following constraints also apply to this encoding: cond != 1111 && o0:D:o1 != 1x11 && cond != 1111

Decode fields Instruction Details
o0:o1 size o2
!= 111 00 UNALLOCATED
000 0 VMLA (floating-point)
000 1 VMLS (floating-point)
001 0 VNMLS
001 1 VNMLA
010 0 VMUL (floating-point)
010 1 VNMUL
011 0 VADD (floating-point)
011 1 VSUB (floating-point)
100 0 VDIV
101 0 VFNMS
101 1 VFNMA
110 0 VFMA
110 1 VFMS

System register 32-bit move

These instructions are under System register access, Advanced SIMD, floating-point, and Supervisor call.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 1 1 1 0 opc1 L CRn Rt 1 1 1 cp15 opc2 1 CRm
Decode fields Instruction Details
cond L
!= 1111 0 MCR
!= 1111 1 MRC
1111 UNALLOCATED

Supervisor call

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cond 1111
Decode fields Instruction details
cond
1111 UNALLOCATED
!= 1111 SVC

Advanced SIMD three registers of the same length extension

These instructions are under System register access, Advanced SIMD, floating-point, and Supervisor call.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 0 op1 D op2 Vn Vd 1 op3 0 op4 N Q M U Vm
Decode fields Instruction Details Architecture Version
op1 op2 op3 op4 Q U
x1 0x 0 0 0 VCADD Armv8.3
00 10 0 0 1 VFMAL (vector) Armv8.2
00 10 1 1 0 0 VSDOT (vector)64-bit SIMD vector Armv8.2
00 10 1 1 0 1 VUDOT (vector)64-bit SIMD vector Armv8.2
00 10 1 1 1 0 VSDOT (vector)128-bit SIMD vector Armv8.2
00 10 1 1 1 1 VUDOT (vector)128-bit SIMD vector Armv8.2
01 10 0 0 1 VFMSL (vector) Armv8.2
1x 0 0 0 VCMLA Armv8.3

Advanced SIMD two registers and a scalar extension

These instructions are under System register access, Advanced SIMD, floating-point, and Supervisor call.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 0 op1 D op2 Vn Vd 1 op3 0 op4 N Q M U Vm
Decode fields Instruction Details Architecture Version
op1 op2 op3 op4 Q U
0 0 0 0 VCMLA (by element)half-precision scalar Armv8.3
0 00 0 0 1 VFMAL (by scalar) Armv8.2
0 01 0 0 1 VFMSL (by scalar) Armv8.2
0 10 1 1 0 0 VSDOT (by element)64-bit SIMD vector Armv8.2
0 10 1 1 0 1 VUDOT (by element)64-bit SIMD vector Armv8.2
0 10 1 1 1 0 VSDOT (by element)128-bit SIMD vector Armv8.2
0 10 1 1 1 1 VUDOT (by element)128-bit SIMD vector Armv8.2
1 0 0 0 VCMLA (by element)single-precision scalar Armv8.3

Advanced SIMD load/store and 64-bit move

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!= 1111 110 op0 10

Advanced SIMD and floating-point 64-bit move

These instructions are under Advanced SIMD load/store and 64-bit move.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 1 1 0 0 0 D 0 op Rt2 Rt 1 0 size opc2 M o3 Vm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111


Advanced SIMD and floating-point load/store

These instructions are under Advanced SIMD load/store and 64-bit move.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 1 1 0 P U D W L Rn Vd 1 0 size imm8
cond

The following constraints also apply to this encoding: cond != 1111 && P:U:D:W != 00x0 && cond != 1111

Decode fields Instruction Details
P U W L Rn size imm8
0 0 1 UNALLOCATED
0 1 0x UNALLOCATED
0 1 0 10 VSTM, VSTMDB, VSTMIA
0 1 0 11 xxxxxxx0 VSTM, VSTMDB, VSTMIA
0 1 0 11 xxxxxxx1 FSTMDBX, FSTMIAXIncrement After
0 1 1 10 VLDM, VLDMDB, VLDMIA
0 1 1 11 xxxxxxx0 VLDM, VLDMDB, VLDMIA
0 1 1 11 xxxxxxx1 FLDM*X (FLDMDBX, FLDMIAX)Increment After
1 0 0 VSTR
1 0 00 UNALLOCATED
1 0 1 != 1111 VLDR (immediate)
1 0 1 0x UNALLOCATED
1 0 1 0 10 VSTM, VSTMDB, VSTMIA
1 0 1 0 11 xxxxxxx0 VSTM, VSTMDB, VSTMIA
1 0 1 0 11 xxxxxxx1 FSTMDBX, FSTMIAXDecrement Before
1 0 1 1 10 VLDM, VLDMDB, VLDMIA
1 0 1 1 11 xxxxxxx0 VLDM, VLDMDB, VLDMIA
1 0 1 1 11 xxxxxxx1 FLDM*X (FLDMDBX, FLDMIAX)Decrement Before
1 0 1 1111 VLDR (literal)
1 1 1 UNALLOCATED

Advanced SIMD and floating-point 32-bit move

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 1110 op0 101 op1 11111

Floating-point move special register

These instructions are under Advanced SIMD and floating-point 32-bit move.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 1 1 1 0 1 1 1 L reg Rt 1 0 1 0 (0) (0) (0) 1 (0) (0) (0) (0)
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
L
0 VMSR
1 VMRS

Advanced SIMD 8/16/32-bit element move/duplicate

These instructions are under Advanced SIMD and floating-point 32-bit move.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 1 1 1 0 opc1 L Vn Rt 1 0 1 1 N opc2 1 (0) (0) (0) (0)
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc1 L opc2
0xx 0 VMOV (general-purpose register to scalar)
1 VMOV (scalar to general-purpose register)
1xx 0 0x VDUP (general-purpose register)
1xx 0 1x UNALLOCATED