You copied the Doc URL to your clipboard.

Unconditional instructions

These instructions are under the top-level.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
11110 op0 op1
Decode fields Instruction details
op0 op1
00 Miscellaneous
01 Advanced SIMD data-processing
1x 1 Memory hints and barriers
10 0 Advanced SIMD element or structure load/store
11 0 UNALLOCATED

Miscellaneous

These instructions are under Unconditional instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1111000 op0 op1
Decode fields Instruction details Architecture version
op0 op1
0xxxx UNALLOCATED -
10000 xx0x Change Process State -
10001 1000 UNALLOCATED -
10001 x100 UNALLOCATED -
10001 xx01 UNALLOCATED -
10001 0000 SETPAN Armv8.1
1000x 0111 UNALLOCATED -
10010 0111 CONSTRAINED UNPREDICTABLE -
10011 0111 UNALLOCATED -
1001x xx0x UNALLOCATED -
100xx 0011 UNALLOCATED -
100xx 0x10 UNALLOCATED -
100xx 1x1x UNALLOCATED -
101xx UNALLOCATED -
11xxx UNALLOCATED -

The behavior of the CONSTRAINED UNPREDICTABLE encodings in this table is described in CONSTRAINED UNPREDICTABLE behavior for A32 and T32 instruction encodings


Change Process State

These instructions are under Miscellaneous.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 0 1 0 0 0 0 imod M op (0) (0) (0) (0) (0) (0) E A I F 0 mode
Decode fields Instruction Details
imod M op mode
1 0xxxx SETEND
0 CPS, CPSID, CPSIE
1 1xxxx UNALLOCATED

Advanced SIMD data-processing

These instructions are under Unconditional instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1111001 op0 op1

Advanced SIMD three registers of the same length

These instructions are under Advanced SIMD data-processing.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 U 0 D size Vn Vd opc N Q M o1 Vm
Decode fields Instruction Details Architecture Version
U size opc Q o1
0 0x 1100 1 VFMA -
0 0x 1101 0 VADD (floating-point) -
0 0x 1101 1 VMLA (floating-point) -
0 0x 1110 0 VCEQ (register)A2 -
0 0x 1111 0 VMAX (floating-point) -
0 0x 1111 1 VRECPS -
0000 0 VHADD -
0 00 0001 1 VAND (register) -
0000 1 VQADD -
0001 0 VRHADD -
0 00 1100 0 SHA1C -
0010 0 VHSUB -
0 01 0001 1 VBIC (register) -
0010 1 VQSUB -
0011 0 VCGT (register)A1 -
0011 1 VCGE (register)A1 -
0 01 1100 0 SHA1P -
0 1x 1100 1 VFMS -
0 1x 1101 0 VSUB (floating-point) -
0 1x 1101 1 VMLS (floating-point) -
0 1x 1110 0 UNALLOCATED -
0 1x 1111 0 VMIN (floating-point) -
0 1x 1111 1 VRSQRTS -
0100 0 VSHL (register) -
0 1000 0 VADD (integer) -
0 10 0001 1 VORR (register) -
0 1000 1 VTST -
0100 1 VQSHL (register) -
0 1001 0 VMLA (integer) -
0101 0 VRSHL -
0101 1 VQRSHL -
0 1011 0 VQDMULH -
0 10 1100 0 SHA1M -
0 1011 1 VPADD (integer) -
0110 0 VMAX (integer) -
0 11 0001 1 VORN (register) -
0110 1 VMIN (integer) -
0111 0 VABD (integer) -
0111 1 VABA -
0 11 1100 0 SHA1SU0 -
1 0x 1101 0 VPADD (floating-point) -
1 0x 1101 1 VMUL (floating-point) -
1 0x 1110 0 VCGE (register)A2 -
1 0x 1110 1 VACGE -
1 0x 1111 0 0 VPMAX (floating-point) -
1 0x 1111 1 VMAXNM -
1 00 0001 1 VEOR -
1001 1 VMUL (integer and polynomial) -
1 00 1100 0 SHA256H -
1010 0 0 VPMAX (integer) -
1 01 0001 1 VBSL -
1010 0 1 VPMIN (integer) -
1010 1 UNALLOCATED -
1 01 1100 0 SHA256H2 -
1 1x 1101 0 VABD (floating-point) -
1 1x 1110 0 VCGT (register)A2 -
1 1x 1110 1 VACGT -
1 1x 1111 0 0 VPMIN (floating-point) -
1 1x 1111 1 VMINNM -
1 1000 0 VSUB (integer) -
1 10 0001 1 VBIT -
1 1000 1 VCEQ (register)A1 -
1 1001 0 VMLS (integer) -
1 1011 0 VQRDMULH -
1 10 1100 0 SHA256SU1 -
1 1011 1 VQRDMLAH Armv8.1
1 11 0001 1 VBIF -
1 1100 1 VQRDMLSH Armv8.1
1 1111 1 0 UNALLOCATED -

Advanced SIMD two registers, or three registers of different lengths

These instructions are under Advanced SIMD data-processing.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1111001 op0 1 op1 op2 op3 0

Advanced SIMD two registers misc

These instructions are under Advanced SIMD two registers, or three registers of different lengths.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1 1 D 1 1 size opc1 Vd 0 opc2 Q M 0 Vm
Decode fields Instruction Details
size opc1 opc2 Q
00 0000 VREV64
00 0001 VREV32
00 0010 VREV16
00 0011 UNALLOCATED
00 010x VPADDL
00 0110 0 AESE
00 0110 1 AESD
00 0111 0 AESMC
00 0111 1 AESIMC
00 1000 VCLS
00 10 0000 VSWP
00 1001 VCLZ
00 1010 VCNT
00 1011 VMVN (register)
00 110x VPADAL
00 1110 VQABS
00 1111 VQNEG
01 x000 VCGT (immediate #0)
01 x001 VCGE (immediate #0)
01 x010 VCEQ (immediate #0)
01 x011 VCLE (immediate #0)
01 x100 VCLT (immediate #0)
01 x110 VABS
01 x111 VNEG
01 0101 1 SHA1H
10 0001 VTRN
10 0010 VUZP
10 0011 VZIP
10 0100 0 VMOVN
10 0100 1 VQMOVN, VQMOVUNVQMOVUN
10 0101 VQMOVN, VQMOVUNVQMOVN
10 0110 0 VSHLL
10 0111 0 SHA1SU1
10 0111 1 SHA256SU0
10 1000 VRINTN (Advanced SIMD)
10 1001 VRINTX (Advanced SIMD)
10 1010 VRINTA (Advanced SIMD)
10 1011 VRINTZ (Advanced SIMD)
10 1100 0 VCVT (between half-precision and single-precision, Advanced SIMD)single-precision to half-precision
10 1100 1 UNALLOCATED
10 1101 VRINTM (Advanced SIMD)
10 1110 0 VCVT (between half-precision and single-precision, Advanced SIMD)half-precision to single-precision
10 1110 1 UNALLOCATED
10 1111 VRINTP (Advanced SIMD)
11 000x VCVTA (Advanced SIMD)
11 001x VCVTN (Advanced SIMD)
11 010x VCVTP (Advanced SIMD)
11 011x VCVTM (Advanced SIMD)
11 10x0 VRECPE
11 10x1 VRSQRTE
11 11xx VCVT (between floating-point and integer, Advanced SIMD)

Advanced SIMD duplicate (scalar)

These instructions are under Advanced SIMD two registers, or three registers of different lengths.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1 1 D 1 1 imm4 Vd 1 1 opc Q M 0 Vm
Decode fields Instruction Details
opc
000 VDUP (scalar)
001 UNALLOCATED
01x UNALLOCATED
1xx UNALLOCATED

Advanced SIMD three registers of different lengths

These instructions are under Advanced SIMD two registers, or three registers of different lengths.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 U 1 D != 11 Vn Vd opc N 0 M 0 Vm
size

The following constraints also apply to this encoding: size != 11 && size != 11

Decode fields Instruction Details
U opc
0000 VADDL
0001 VADDW
0010 VSUBL
0 0100 VADDHN
0011 VSUBW
0 0110 VSUBHN
0 1001 VQDMLAL
0101 VABAL
0 1011 VQDMLSL
0 1101 VQDMULL
0111 VABDL (integer)
1000 VMLAL (integer)
1010 VMLSL (integer)
1 0100 VRADDHN
1 0110 VRSUBHN
11x0 VMULL (integer and polynomial)
1 1001 UNALLOCATED
1 1011 UNALLOCATED
1 1101 UNALLOCATED
1111 UNALLOCATED

Advanced SIMD two registers and a scalar

These instructions are under Advanced SIMD two registers, or three registers of different lengths.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 Q 1 D != 11 Vn Vd opc N 1 M 0 Vm
size

The following constraints also apply to this encoding: size != 11 && size != 11

Decode fields Instruction Details Architecture Version
Q opc
000x VMLA (by scalar) -
0 0011 VQDMLAL -
0010 VMLAL (by scalar) -
0 0111 VQDMLSL -
010x VMLS (by scalar) -
0 1011 VQDMULL -
0110 VMLSL (by scalar) -
100x VMUL (by scalar) -
1 0011 UNALLOCATED -
1010 VMULL (by scalar) -
1 0111 UNALLOCATED -
1100 VQDMULH -
1101 VQRDMULH -
1 1011 UNALLOCATED -
1110 VQRDMLAH Armv8.1
1111 VQRDMLSH Armv8.1

Advanced SIMD shifts and immediate generation

These instructions are under Advanced SIMD data-processing.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1111001 1 op0 1
Decode fields Instruction details
op0
000xxxxxxxxxxx0 Advanced SIMD one register and modified immediate
!= 000xxxxxxxxxxx0 Advanced SIMD two registers and shift amount

Advanced SIMD one register and modified immediate

These instructions are under Advanced SIMD shifts and immediate generation.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode 0 Q op 1 imm4
Decode fields Instruction Details
cmode op
0xx0 0 VMOV (immediate)A1
0xx0 1 VMVN (immediate)A1
0xx1 0 VORR (immediate)A1
0xx1 1 VBIC (immediate)A1
10x0 0 VMOV (immediate)A3
10x0 1 VMVN (immediate)A2
10x1 0 VORR (immediate)A2
10x1 1 VBIC (immediate)A2
11xx 0 VMOV (immediate)A4
110x 1 VMVN (immediate)A3
1110 1 VMOV (immediate)A5
1111 1 UNALLOCATED

Advanced SIMD two registers and shift amount

These instructions are under Advanced SIMD shifts and immediate generation.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 U 1 D imm3H imm3L Vd opc L Q M 1 Vm

The following constraints also apply to this encoding: imm3H:imm3L:Vd:opc:L != 000xxxxxxxxxxx0

Decode fields Instruction Details
U imm3H:L imm3L opc Q
!= 0000 0000 VSHR
!= 0000 0001 VSRA
!= 0000 000 1010 0 VMOVL
!= 0000 0010 VRSHR
!= 0000 0011 VRSRA
!= 0000 0111 VQSHL, VQSHLU (immediate)VQSHL
!= 0000 1001 0 VQSHRN, VQSHRUNVQSHRN
!= 0000 1001 1 VQRSHRN, VQRSHRUNVQRSHRN
!= 0000 1010 0 VSHLL
!= 0000 11xx VCVT (between floating-point and fixed-point, Advanced SIMD)
0 != 0000 0101 VSHL (immediate)
0 != 0000 1000 0 VSHRN
0 != 0000 1000 1 VRSHRN
1 != 0000 0100 VSRI
1 != 0000 0101 VSLI
1 != 0000 0110 VQSHL, VQSHLU (immediate)VQSHLU
1 != 0000 1000 0 VQSHRN, VQSHRUNVQSHRUN
1 != 0000 1000 1 VQRSHRN, VQRSHRUNVQRSHRUN

Memory hints and barriers

These instructions are under Unconditional instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
111101 op0 1 op1
Decode fields Instruction details
op0 op1
00xx1 CONSTRAINED UNPREDICTABLE
01001 CONSTRAINED UNPREDICTABLE
01011 Barriers
011x1 CONSTRAINED UNPREDICTABLE
0xxx0 Preload (immediate)
1xxx0 0 Preload (register)
1xxx1 0 CONSTRAINED UNPREDICTABLE
1xxxx 1 UNALLOCATED

The behavior of the CONSTRAINED UNPREDICTABLE encodings in this table is described in CONSTRAINED UNPREDICTABLE behavior for A32 and T32 instruction encodings


Barriers

These instructions are under Memory hints and barriers.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 0 1 0 1 1 1 (1) (1) (1) (1) (1) (1) (1) (1) (0) (0) (0) (0) opcode option
Decode fields Instruction Details
opcode option
0000 CONSTRAINED UNPREDICTABLE
0001 CLREX
001x CONSTRAINED UNPREDICTABLE
0100 DSB
0100 0000 SSBB
0100 0100 PSSBB
0101 DMB
0110 ISB
0111 SB
1xxx CONSTRAINED UNPREDICTABLE

The behavior of the CONSTRAINED UNPREDICTABLE encodings in this table is described in CONSTRAINED UNPREDICTABLE behavior for A32 and T32 instruction encodings


Preload (immediate)

These instructions are under Memory hints and barriers.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 0 D U R 0 1 Rn (1) (1) (1) (1) imm12
Decode fields Instruction Details
D R Rn
0 0 Reserved hint, behaves as NOP
0 1 PLI (immediate, literal)
1 1111 PLD (literal)
1 0 != 1111 PLD, PLDW (immediate)preload write
1 1 != 1111 PLD, PLDW (immediate)preload read

Preload (register)

These instructions are under Memory hints and barriers.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 1 D U o2 0 1 Rn (1) (1) (1) (1) imm5 type 0 Rm
Decode fields Instruction Details
D o2
0 0 Reserved hint, behaves as NOP
0 1 PLI (register)
1 0 PLD, PLDW (register)preload write
1 1 PLD, PLDW (register)preload read

Advanced SIMD element or structure load/store

These instructions are under Unconditional instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
11110100 op0 0 op1

Advanced SIMD load/store multiple structures

These instructions are under Advanced SIMD element or structure load/store.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 0 0 0 D L 0 Rn Vd type size align Rm

Advanced SIMD load single structure to all lanes

These instructions are under Advanced SIMD element or structure load/store.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 0 0 1 D L 0 Rn Vd 1 1 N size T a Rm

Advanced SIMD load/store single structure to one lane

These instructions are under Advanced SIMD element or structure load/store.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 0 0 1 D L 0 Rn Vd != 11 N index_align Rm
size

The following constraints also apply to this encoding: size != 11 && size != 11