Arm® A32/T32 Instruction Set Architecture: Armv8, for Armv8-A architecture profile Documentation

MRS

Move Special register to general-purpose register moves the value of the APSR, CPSR, or SPSR_<current_mode> into a general-purpose register.

Arm recommends the APSR form when only the N, Z, C, V, Q, and GE[3:0] bits are being written. For more information, see APSR.

An MRS that accesses the SPSRs is unpredictable if executed in User mode or System mode.

An MRS that is executed in User mode and accesses the CPSR returns an unknown value for the CPSR.{E, A, I, F, M} fields.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

d = UInt(Rd);  read_spsr = (R == '1');
if d == 15 then UNPREDICTABLE;

T1

d = UInt(Rd);  read_spsr = (R == '1');
if d == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

if ConditionPassed() then
    EncodingSpecificOperations();
    if read_spsr then
        if PSTATE.M IN {M32_User,M32_System} then
            UNPREDICTABLE;
        else
            R[d] = SPSR[];
    else
        // CPSR has same bit assignments as SPSR, but with the IT, J, SS, IL, and T bits masked out.
        bits(32) mask = '11111000 00001111 00000011 11011111';
        if HavePANExt() then
            mask<22> = '1';
        psr_val = GetPSRFromPSTATE() AND mask;
        if PSTATE.EL == EL0 then
            // If accessed from User mode return UNKNOWN values for E, A, I, F bits, bits<9:6>,
            // and for the M field, bits<4:0>
            psr_val<22> = bits(1) UNKNOWN;
            psr_val<9:6> = bits(4) UNKNOWN;
            psr_val<4:0> = bits(5) UNKNOWN;
        R[d] = psr_val;

CONSTRAINED UNPREDICTABLE behavior

If PSTATE.M IN {M32_User, M32_System} && read_spsr, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.