MSR (register)
Move general-purpose register to Special register moves selected bits of a general-purpose register to the APSR, CPSR or SPSR_<current_mode>.
Because of the Do-Not-Modify nature of its reserved bits, a read-modify-write sequence is normally required when the MSR instruction is being used at Application level and its destination is not APSR_nzcvq (CPSR_f).
If an MSR (register) moves selected bits of an immediate value to the CPSR, the PE checks whether the value being written to PSTATE.M is legal. See Illegal changes to PSTATE.M.
An MSR (register) executed in User mode:
- Is unpredictable if it attempts to update the SPSR.
- Otherwise, does not update any CPSR field that is accessible only at EL1 or higher.
An MSR (register) executed in System mode is unpredictable if it attempts to update the SPSR.
The CPSR.E bit is writable from any mode using an MSR instruction. Arm deprecates using this to change its value.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
A1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 0 | 0 | 0 | 1 | 0 | R | 1 | 0 | mask | (1) | (1) | (1) | (1) | (0) | (0) | 0 | (0) | 0 | 0 | 0 | 0 | Rn | |||||||||
cond |
A1
MSR{<c>}{<q>} <spec_reg>, <Rn>
n = UInt(Rn); write_spsr = (R == '1'); if mask == '0000' then UNPREDICTABLE; if n == 15 then UNPREDICTABLE;
CONSTRAINED UNPREDICTABLE behavior
If mask == '0000', then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
T1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | R | Rn | 1 | 0 | (0) | 0 | mask | (0) | (0) | 0 | (0) | (0) | (0) | (0) | (0) |
T1
MSR{<c>}{<q>} <spec_reg>, <Rn>
n = UInt(Rn); write_spsr = (R == '1'); if mask == '0000' then UNPREDICTABLE; if n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13
CONSTRAINED UNPREDICTABLE behavior
If mask == '0000', then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
Assembler Symbols
<c> |
<q> |
<spec_reg> |
Is one of:
For CPSR and SPSR, <fields> is a sequence of one or more of the following:
For APSR, <bits> is one of nzcvq, g, or nzcvqg. These map to the following CPSR_<fields> values:
Arm recommends the APSR_<bits> forms when only the N, Z, C, V, Q, and GE[3:0] bits are being written. For more information, see The Application Program Status Register, APSR. |
<Rn> |
Is the general-purpose source register, encoded in the "Rn" field. |
Operation
if ConditionPassed() then EncodingSpecificOperations(); if write_spsr then if PSTATE.M IN {M32_User,M32_System} then UNPREDICTABLE; else SPSRWriteByInstr(R[n], mask); else // Attempts to change to an illegal mode will invoke the Illegal Execution state mechanism CPSRWriteByInstr(R[n], mask);
CONSTRAINED UNPREDICTABLE behavior
If write_spsr && PSTATE.M IN {M32_User,M32_System}, then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.