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## VCLE (register)

Vector Compare Less Than or Equal takes each element in a vector, and compares it with the corresponding element of a second vector. If the first is less than or equal to the second, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.

This is a pseudo-instruction of VCGE (register). This means:

• The encodings in this description are named to match the encodings of VCGE (register).
• The assembler syntax is used only for assembly, and is not used on disassembly.
• The description of VCGE (register) gives the operational pseudocode for this instruction.

It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 and T2 ) .

### A1

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 0 1 1 N Q M 1 Vm

#### 64-bit SIMD vector (Q == 0)

VCLE{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>

is equivalent to

VCGE{<c>}{<q>}.<dt> <Dd>, <Dm>, <Dn>

#### 128-bit SIMD vector (Q == 1)

VCLE{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>

is equivalent to

VCGE{<c>}{<q>}.<dt> <Qd>, <Qm>, <Qn>

### A2

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 0 0 1 1 0 D 0 sz Vn Vd 1 1 1 0 N Q M 0 Vm

#### 64-bit SIMD vector (Q == 0)

VCLE{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>

is equivalent to

VCGE{<c>}{<q>}.<dt> <Dd>, <Dm>, <Dn>

#### 128-bit SIMD vector (Q == 1)

VCLE{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>

is equivalent to

VCGE{<c>}{<q>}.<dt> <Qd>, <Qm>, <Qn>

### T1

 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 U 1 1 1 1 0 D size Vn Vd 0 0 1 1 N Q M 1 Vm

#### 64-bit SIMD vector (Q == 0)

VCLE{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>

is equivalent to

VCGE{<c>}{<q>}.<dt> <Dd>, <Dm>, <Dn>

#### 128-bit SIMD vector (Q == 1)

VCLE{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>

is equivalent to

VCGE{<c>}{<q>}.<dt> <Qd>, <Qm>, <Qn>

### T2

 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 0 D 0 sz Vn Vd 1 1 1 0 N Q M 0 Vm

#### 64-bit SIMD vector (Q == 0)

VCLE{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>

is equivalent to

VCGE{<c>}{<q>}.<dt> <Dd>, <Dm>, <Dn>

#### 128-bit SIMD vector (Q == 1)

VCLE{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>

is equivalent to

VCGE{<c>}{<q>}.<dt> <Qd>, <Qm>, <Qn>

### Assembler Symbols

 Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
 Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
 Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as *2.
 Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as *2.
 For encoding A1 and A2: see Standard assembler syntax fields. This encoding must be unconditional. For encoding T1 and T2: see Standard assembler syntax fields.

<dt> For encoding A1 and T1: is the data type for the elements of the operands, encoded in U:size:
U size <dt>
0 00 S8
0 01 S16
0 10 S32
1 00 U8
1 01 U16
1 10 U32
For encoding A2 and T2: is the data type for the elements of the vectors, encoded in sz:
sz <dt>
0 F32
1 F16
 Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as *2.

Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

### Operation

The description of VCGE (register) gives the operational pseudocode for this instruction.