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- AESD: AES single round decryption.
- AESE: AES single round encryption.
- AESIMC: AES inverse mix columns.
- AESMC: AES mix columns.
- FLDM*X (FLDMDBX, FLDMIAX): FLDM*X.
- FSTMDBX, FSTMIAX: FSTMX.
- SHA1C: SHA1 hash update (choose).
- SHA1H: SHA1 fixed rotate.
- SHA1M: SHA1 hash update (majority).
- SHA1P: SHA1 hash update (parity).
- SHA1SU0: SHA1 schedule update 0.
- SHA1SU1: SHA1 schedule update 1.
- SHA256H: SHA256 hash update part 1.
- SHA256H2: SHA256 hash update part 2.
- SHA256SU0: SHA256 schedule update 0.
- SHA256SU1: SHA256 schedule update 1.
- VABA: Vector Absolute Difference and Accumulate.
- VABAL: Vector Absolute Difference and Accumulate Long.
- VABD (floating-point): Vector Absolute Difference (floating-point).
- VABD (integer): Vector Absolute Difference (integer).
- VABDL (integer): Vector Absolute Difference Long (integer).
- VABS: Vector Absolute.
- VACGE: Vector Absolute Compare Greater Than or Equal.
- VACGT: Vector Absolute Compare Greater Than.
- VACLE: Vector Absolute Compare Less Than or Equal: an alias of VACGE.
- VACLT: Vector Absolute Compare Less Than: an alias of VACGT.
- VADD (floating-point): Vector Add (floating-point).
- VADD (integer): Vector Add (integer).
- VADDHN: Vector Add and Narrow, returning High Half.
- VADDL: Vector Add Long.
- VADDW: Vector Add Wide.
- VAND (immediate): Vector Bitwise AND (immediate): an alias of VBIC (immediate).
- VAND (register): Vector Bitwise AND (register).
- VBIC (immediate): Vector Bitwise Bit Clear (immediate).
- VBIC (register): Vector Bitwise Bit Clear (register).
- VBIF: Vector Bitwise Insert if False.
- VBIT: Vector Bitwise Insert if True.
- VBSL: Vector Bitwise Select.
- VCADD: Vector Complex Add.
- VCEQ (immediate #0): Vector Compare Equal to Zero.
- VCEQ (register): Vector Compare Equal.
- VCGE (immediate #0): Vector Compare Greater Than or Equal to Zero.
- VCGE (register): Vector Compare Greater Than or Equal.
- VCGT (immediate #0): Vector Compare Greater Than Zero.
- VCGT (register): Vector Compare Greater Than.
- VCLE (immediate #0): Vector Compare Less Than or Equal to Zero.
- VCLE (register): Vector Compare Less Than or Equal: an alias of VCGE (register).
- VCLS: Vector Count Leading Sign Bits.
- VCLT (immediate #0): Vector Compare Less Than Zero.
- VCLT (register): Vector Compare Less Than: an alias of VCGT (register).
- VCLZ: Vector Count Leading Zeros.
- VCMLA: Vector Complex Multiply Accumulate.
- VCMLA (by element): Vector Complex Multiply Accumulate (by element).
- VCMP: Vector Compare.
- VCMPE: Vector Compare, raising Invalid Operation on NaN.
- VCNT: Vector Count Set Bits.
- VCVT (between double-precision and single-precision): Convert between double-precision and single-precision.
- VCVT (between floating-point and fixed-point, Advanced SIMD): Vector Convert between floating-point and fixed-point.
- VCVT (between floating-point and fixed-point, floating-point): Convert between floating-point and fixed-point.
- VCVT (between floating-point and integer, Advanced SIMD): Vector Convert between floating-point and integer.
- VCVT (between half-precision and single-precision, Advanced SIMD): Vector Convert between half-precision and single-precision.
- VCVT (floating-point to integer, floating-point): Convert floating-point to integer with Round towards Zero.
- VCVT (integer to floating-point, floating-point): Convert integer to floating-point.
- VCVTA (Advanced SIMD): Vector Convert floating-point to integer with Round to Nearest with Ties to Away.
- VCVTA (floating-point): Convert floating-point to integer with Round to Nearest with Ties to Away.
- VCVTB: Convert to or from a half-precision value in the bottom half of a single-precision register.
- VCVTM (Advanced SIMD): Vector Convert floating-point to integer with Round towards -Infinity.
- VCVTM (floating-point): Convert floating-point to integer with Round towards -Infinity.
- VCVTN (Advanced SIMD): Vector Convert floating-point to integer with Round to Nearest.
- VCVTN (floating-point): Convert floating-point to integer with Round to Nearest.
- VCVTP (Advanced SIMD): Vector Convert floating-point to integer with Round towards +Infinity.
- VCVTP (floating-point): Convert floating-point to integer with Round towards +Infinity.
- VCVTR: Convert floating-point to integer.
- VCVTT: Convert to or from a half-precision value in the top half of a single-precision register.
- VDIV: Divide.
- VDUP (general-purpose register): Duplicate general-purpose register to vector.
- VDUP (scalar): Duplicate vector element to vector.
- VEOR: Vector Bitwise Exclusive OR.
- VEXT (byte elements): Vector Extract.
- VEXT (multibyte elements): Vector Extract: an alias of VEXT (byte elements).
- VFMA: Vector Fused Multiply Accumulate.
- VFMAL (by scalar): Vector Floating-point Multiply-Add Long to accumulator (by scalar).
- VFMAL (vector): Vector Floating-point Multiply-Add Long to accumulator (vector).
- VFMS: Vector Fused Multiply Subtract.
- VFMSL (by scalar): Vector Floating-point Multiply-Subtract Long from accumulator (by scalar).
- VFMSL (vector): Vector Floating-point Multiply-Subtract Long from accumulator (vector).
- VFNMA: Vector Fused Negate Multiply Accumulate.
- VFNMS: Vector Fused Negate Multiply Subtract.
- VHADD: Vector Halving Add.
- VHSUB: Vector Halving Subtract.
- VINS: Vector move Insertion.
- VJCVT: Javascript Convert to signed fixed-point, rounding toward Zero.
- VLD1 (multiple single elements): Load multiple single 1-element structures to one, two, three, or four registers.
- VLD1 (single element to all lanes): Load single 1-element structure and replicate to all lanes of one register.
- VLD1 (single element to one lane): Load single 1-element structure to one lane of one register.
- VLD2 (multiple 2-element structures): Load multiple 2-element structures to two or four registers.
- VLD2 (single 2-element structure to all lanes): Load single 2-element structure and replicate to all lanes of two registers.
- VLD2 (single 2-element structure to one lane): Load single 2-element structure to one lane of two registers.
- VLD3 (multiple 3-element structures): Load multiple 3-element structures to three registers.
- VLD3 (single 3-element structure to all lanes): Load single 3-element structure and replicate to all lanes of three registers.
- VLD3 (single 3-element structure to one lane): Load single 3-element structure to one lane of three registers.
- VLD4 (multiple 4-element structures): Load multiple 4-element structures to four registers.
- VLD4 (single 4-element structure to all lanes): Load single 4-element structure and replicate to all lanes of four registers.
- VLD4 (single 4-element structure to one lane): Load single 4-element structure to one lane of four registers.
- VLDM, VLDMDB, VLDMIA: Load Multiple SIMD&FP registers.
- VLDR (immediate): Load SIMD&FP register (immediate).
- VLDR (literal): Load SIMD&FP register (literal).
- VMAX (floating-point): Vector Maximum (floating-point).
- VMAX (integer): Vector Maximum (integer).
- VMAXNM: Floating-point Maximum Number.
- VMIN (floating-point): Vector Minimum (floating-point).
- VMIN (integer): Vector Minimum (integer).
- VMINNM: Floating-point Minimum Number.
- VMLA (by scalar): Vector Multiply Accumulate (by scalar).
- VMLA (floating-point): Vector Multiply Accumulate (floating-point).
- VMLA (integer): Vector Multiply Accumulate (integer).
- VMLAL (by scalar): Vector Multiply Accumulate Long (by scalar).
- VMLAL (integer): Vector Multiply Accumulate Long (integer).
- VMLS (by scalar): Vector Multiply Subtract (by scalar).
- VMLS (floating-point): Vector Multiply Subtract (floating-point).
- VMLS (integer): Vector Multiply Subtract (integer).
- VMLSL (by scalar): Vector Multiply Subtract Long (by scalar).
- VMLSL (integer): Vector Multiply Subtract Long (integer).
- VMOV (between general-purpose register and half-precision): Copy 16 bits of a general-purpose register to or from a 32-bit SIMD&FP register.
- VMOV (between general-purpose register and single-precision): Copy a general-purpose register to or from a 32-bit SIMD&FP register.
- VMOV (between two general-purpose registers and a doubleword floating-point register): Copy two general-purpose registers to or from a SIMD&FP register.
- VMOV (between two general-purpose registers and two single-precision registers): Copy two general-purpose registers to a pair of 32-bit SIMD&FP registers.
- VMOV (general-purpose register to scalar): Copy a general-purpose register to a vector element.
- VMOV (immediate): Copy immediate value to a SIMD&FP register.
- VMOV (register): Copy between FP registers.
- VMOV (register, SIMD): Copy between SIMD registers: an alias of VORR (register).
- VMOV (scalar to general-purpose register): Copy a vector element to a general-purpose register with sign or zero extension.
- VMOVL: Vector Move Long.
- VMOVN: Vector Move and Narrow.
- VMOVX: Vector Move extraction.
- VMRS: Move SIMD&FP Special register to general-purpose register.
- VMSR: Move general-purpose register to SIMD&FP Special register.
- VMUL (by scalar): Vector Multiply (by scalar).
- VMUL (floating-point): Vector Multiply (floating-point).
- VMUL (integer and polynomial): Vector Multiply (integer and polynomial).
- VMULL (by scalar): Vector Multiply Long (by scalar).
- VMULL (integer and polynomial): Vector Multiply Long (integer and polynomial).
- VMVN (immediate): Vector Bitwise NOT (immediate).
- VMVN (register): Vector Bitwise NOT (register).
- VNEG: Vector Negate.
- VNMLA: Vector Negate Multiply Accumulate.
- VNMLS: Vector Negate Multiply Subtract.
- VNMUL: Vector Negate Multiply.
- VORN (immediate): Vector Bitwise OR NOT (immediate): an alias of VORR (immediate).
- VORN (register): Vector bitwise OR NOT (register).
- VORR (immediate): Vector Bitwise OR (immediate).
- VORR (register): Vector bitwise OR (register).
- VPADAL: Vector Pairwise Add and Accumulate Long.
- VPADD (floating-point): Vector Pairwise Add (floating-point).
- VPADD (integer): Vector Pairwise Add (integer).
- VPADDL: Vector Pairwise Add Long.
- VPMAX (floating-point): Vector Pairwise Maximum (floating-point).
- VPMAX (integer): Vector Pairwise Maximum (integer).
- VPMIN (floating-point): Vector Pairwise Minimum (floating-point).
- VPMIN (integer): Vector Pairwise Minimum (integer).
- VPOP: Pop SIMD&FP registers from Stack: an alias of VLDM, VLDMDB, VLDMIA.
- VPUSH: Push SIMD&FP registers to Stack: an alias of VSTM, VSTMDB, VSTMIA.
- VQABS: Vector Saturating Absolute.
- VQADD: Vector Saturating Add.
- VQDMLAL: Vector Saturating Doubling Multiply Accumulate Long.
- VQDMLSL: Vector Saturating Doubling Multiply Subtract Long.
- VQDMULH: Vector Saturating Doubling Multiply Returning High Half.
- VQDMULL: Vector Saturating Doubling Multiply Long.
- VQMOVN, VQMOVUN: Vector Saturating Move and Narrow.
- VQNEG: Vector Saturating Negate.
- VQRDMLAH: Vector Saturating Rounding Doubling Multiply Accumulate Returning High Half.
- VQRDMLSH: Vector Saturating Rounding Doubling Multiply Subtract Returning High Half.
- VQRDMULH: Vector Saturating Rounding Doubling Multiply Returning High Half.
- VQRSHL: Vector Saturating Rounding Shift Left.
- VQRSHRN (zero): Vector Saturating Rounding Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.
- VQRSHRN, VQRSHRUN: Vector Saturating Rounding Shift Right, Narrow.
- VQRSHRUN (zero): Vector Saturating Rounding Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.
- VQSHL (register): Vector Saturating Shift Left (register).
- VQSHL, VQSHLU (immediate): Vector Saturating Shift Left (immediate).
- VQSHRN (zero): Vector Saturating Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.
- VQSHRN, VQSHRUN: Vector Saturating Shift Right, Narrow.
- VQSHRUN (zero): Vector Saturating Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.
- VQSUB: Vector Saturating Subtract.
- VRADDHN: Vector Rounding Add and Narrow, returning High Half.
- VRECPE: Vector Reciprocal Estimate.
- VRECPS: Vector Reciprocal Step.
- VREV16: Vector Reverse in halfwords.
- VREV32: Vector Reverse in words.
- VREV64: Vector Reverse in doublewords.
- VRHADD: Vector Rounding Halving Add.
- VRINTA (Advanced SIMD): Vector Round floating-point to integer towards Nearest with Ties to Away.
- VRINTA (floating-point): Round floating-point to integer to Nearest with Ties to Away.
- VRINTM (Advanced SIMD): Vector Round floating-point to integer towards -Infinity.
- VRINTM (floating-point): Round floating-point to integer towards -Infinity.
- VRINTN (Advanced SIMD): Vector Round floating-point to integer to Nearest.
- VRINTN (floating-point): Round floating-point to integer to Nearest.
- VRINTP (Advanced SIMD): Vector Round floating-point to integer towards +Infinity.
- VRINTP (floating-point): Round floating-point to integer towards +Infinity.
- VRINTR: Round floating-point to integer.
- VRINTX (Advanced SIMD): Vector round floating-point to integer inexact.
- VRINTX (floating-point): Round floating-point to integer inexact.
- VRINTZ (Advanced SIMD): Vector round floating-point to integer towards Zero.
- VRINTZ (floating-point): Round floating-point to integer towards Zero.
- VRSHL: Vector Rounding Shift Left.
- VRSHR: Vector Rounding Shift Right.
- VRSHR (zero): Vector Rounding Shift Right: an alias of VORR (register).
- VRSHRN: Vector Rounding Shift Right and Narrow.
- VRSHRN (zero): Vector Rounding Shift Right and Narrow: an alias of VMOVN.
- VRSQRTE: Vector Reciprocal Square Root Estimate.
- VRSQRTS: Vector Reciprocal Square Root Step.
- VRSRA: Vector Rounding Shift Right and Accumulate.
- VRSUBHN: Vector Rounding Subtract and Narrow, returning High Half.
- VSDOT (by element): Dot Product index form with signed integers..
- VSDOT (vector): Dot Product vector form with signed integers..
- VSELEQ, VSELGE, VSELGT, VSELVS: Floating-point conditional select.
- VSHL (immediate): Vector Shift Left (immediate).
- VSHL (register): Vector Shift Left (register).
- VSHLL: Vector Shift Left Long.
- VSHR: Vector Shift Right.
- VSHR (zero): Vector Shift Right: an alias of VORR (register).
- VSHRN: Vector Shift Right Narrow.
- VSHRN (zero): Vector Shift Right Narrow: an alias of VMOVN.
- VSLI: Vector Shift Left and Insert.
- VSQRT: Square Root.
- VSRA: Vector Shift Right and Accumulate.
- VSRI: Vector Shift Right and Insert.
- VST1 (multiple single elements): Store multiple single elements from one, two, three, or four registers.
- VST1 (single element from one lane): Store single element from one lane of one register.
- VST2 (multiple 2-element structures): Store multiple 2-element structures from two or four registers.
- VST2 (single 2-element structure from one lane): Store single 2-element structure from one lane of two registers.
- VST3 (multiple 3-element structures): Store multiple 3-element structures from three registers.
- VST3 (single 3-element structure from one lane): Store single 3-element structure from one lane of three registers.
- VST4 (multiple 4-element structures): Store multiple 4-element structures from four registers.
- VST4 (single 4-element structure from one lane): Store single 4-element structure from one lane of four registers.
- VSTM, VSTMDB, VSTMIA: Store multiple SIMD&FP registers.
- VSTR: Store SIMD&FP register.
- VSUB (floating-point): Vector Subtract (floating-point).
- VSUB (integer): Vector Subtract (integer).
- VSUBHN: Vector Subtract and Narrow, returning High Half.
- VSUBL: Vector Subtract Long.
- VSUBW: Vector Subtract Wide.
- VSWP: Vector Swap.
- VTBL, VTBX: Vector Table Lookup and Extension.
- VTRN: Vector Transpose.
- VTST: Vector Test Bits.
- VUDOT (by element): Dot Product index form with unsigned integers..
- VUDOT (vector): Dot Product vector form with unsigned integers..
- VUZP: Vector Unzip.
- VUZP (alias): Vector Unzip: an alias of VTRN.
- VZIP: Vector Zip.
- VZIP (alias): Vector Zip: an alias of VTRN.