VCMP
Vector Compare compares two floating-point registers, or one floating-point register and zero. It writes the result to the FPSCR flags. These are normally transferred to the PSTATE.{N, Z, C, V} Condition flags by a subsequent VMRS instruction.
It raises an Invalid Operation exception only if either operand is a signaling NaN.
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 and T2 ) .
A1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | 0 | 1 | 0 | 0 | Vd | 1 | 0 | size | 0 | 1 | M | 0 | Vm | ||||||||||
cond | E |
if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED; if size == '01' && cond != '1110' then UNPREDICTABLE; quiet_nan_exc = (E == '1'); with_zero = FALSE; case size of when '01' esize = 16; d = UInt(Vd:D); m = UInt(Vm:M); when '10' esize = 32; d = UInt(Vd:D); m = UInt(Vm:M); when '11' esize = 64; d = UInt(D:Vd); m = UInt(M:Vm);
CONSTRAINED UNPREDICTABLE behavior
If size == '01' && cond != '1110', then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as if it passes the Condition code check.
- The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
A2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | 0 | 1 | 0 | 1 | Vd | 1 | 0 | size | 0 | 1 | (0) | 0 | (0) | (0) | (0) | (0) | |||||||
cond | E |
if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED; if size == '01' && cond != '1110' then UNPREDICTABLE; quiet_nan_exc = (E == '1'); with_zero = TRUE; case size of when '01' esize = 16; d = UInt(Vd:D); when '10' esize = 32; d = UInt(Vd:D); when '11' esize = 64; d = UInt(D:Vd);
CONSTRAINED UNPREDICTABLE behavior
If size == '01' && cond != '1110', then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as if it passes the Condition code check.
- The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
T1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | 0 | 1 | 0 | 0 | Vd | 1 | 0 | size | 0 | 1 | M | 0 | Vm | |||||||
E |
if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED; if size == '01' && InITBlock() then UNPREDICTABLE; quiet_nan_exc = (E == '1'); with_zero = FALSE; case size of when '01' esize = 16; d = UInt(Vd:D); m = UInt(Vm:M); when '10' esize = 32; d = UInt(Vd:D); m = UInt(Vm:M); when '11' esize = 64; d = UInt(D:Vd); m = UInt(M:Vm);
CONSTRAINED UNPREDICTABLE behavior
If size == '01' && InITBlock(), then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as if it passes the Condition code check.
- The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
T2
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | 0 | 1 | 0 | 1 | Vd | 1 | 0 | size | 0 | 1 | (0) | 0 | (0) | (0) | (0) | (0) | ||||
E |
if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED; if size == '01' && InITBlock() then UNPREDICTABLE; quiet_nan_exc = (E == '1'); with_zero = TRUE; case size of when '01' esize = 16; d = UInt(Vd:D); when '10' esize = 32; d = UInt(Vd:D); when '11' esize = 64; d = UInt(D:Vd);
CONSTRAINED UNPREDICTABLE behavior
If size == '01' && InITBlock(), then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as if it passes the Condition code check.
- The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
Assembler Symbols
<c> |
<q> |
<Sd> |
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field. |
<Sm> |
Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field. |
<Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
<Dm> |
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field. |
NaNs
The IEEE 754 standard specifies that the result of a comparison is precisely one of <, ==, > or unordered. If either or both of the operands are NaNs, they are unordered, and all three of (Operand1 < Operand2), (Operand1 == Operand2) and (Operand1 > Operand2) are false. This results in the FPSCR flags being set as N=0, Z=0, C=1 and V=1.
VCMPE raises an Invalid Operation exception if either operand is any type of NaN, and is suitable for testing for <, <=, >, >=, and other predicates that raise an exception when the operands are unordered.
Operation
if ConditionPassed() then EncodingSpecificOperations(); CheckVFPEnabled(TRUE); bits(4) nzcv; case esize of when 16 bits(16) op16 = if with_zero then FPZero('0') else S[m]<15:0>; nzcv = FPCompare(S[d]<15:0>, op16, quiet_nan_exc, FPSCR); when 32 bits(32) op32 = if with_zero then FPZero('0') else S[m]; nzcv = FPCompare(S[d], op32, quiet_nan_exc, FPSCR); when 64 bits(64) op64 = if with_zero then FPZero('0') else D[m]; nzcv = FPCompare(D[d], op64, quiet_nan_exc, FPSCR); FPSCR.<N,Z,C,V> = nzcv;
Operational information
If CPSR.DIT is 1 and this instruction passes its condition execution check:
- The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.