VCVT (between floatingpoint and fixedpoint, floatingpoint)
Convert between floatingpoint and fixedpoint converts a value in a register from floatingpoint to fixedpoint, or from fixedpoint to floatingpoint. Software can specify the fixedpoint value as either signed or unsigned.
The fixedpoint value can be 16bit or 32bit. Conversions from fixedpoint values take their operand from the loworder bits of the source register and ignore any remaining bits. Signed conversions to fixedpoint values signextend the result value to the destination register width. Unsigned conversions to fixedpoint values zeroextend the result value to the destination register width.
The floatingpoint to fixedpoint operation uses the Round towards Zero rounding mode. The fixedpoint to floatingpoint operation uses the Round to Nearest rounding mode.
Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floatingpoint support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
A1
31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  15  14  13  12  11  10  9  8  7  6  5  4  3  2  1  0 
!= 1111  1  1  1  0  1  D  1  1  1  op  1  U  Vd  1  0  sf  sx  1  i  0  imm4  
cond 
if sf == '00'  (sf == '01' && !HaveFP16Ext()) then UNDEFINED; if sf == '01' && cond != '1110' then UNPREDICTABLE; to_fixed = (op == '1'); unsigned = (U == '1'); size = if sx == '0' then 16 else 32; frac_bits = size  UInt(imm4:i); case sf of when '01' fp_size = 16; d = UInt(Vd:D); when '10' fp_size = 32; d = UInt(Vd:D); when '11' fp_size = 64; d = UInt(D:Vd); if frac_bits < 0 then UNPREDICTABLE;
CONSTRAINED UNPREDICTABLE behavior
If frac_bits < 0, then one of the following behaviors must occur:
 The instruction is undefined.
 The instruction executes as NOP.
 The value in the destination register is unknown.
T1
15  14  13  12  11  10  9  8  7  6  5  4  3  2  1  0  15  14  13  12  11  10  9  8  7  6  5  4  3  2  1  0 
1  1  1  0  1  1  1  0  1  D  1  1  1  op  1  U  Vd  1  0  sf  sx  1  i  0  imm4 
if sf == '00'  (sf == '01' && !HaveFP16Ext()) then UNDEFINED; if sf == '01' && InITBlock() then UNPREDICTABLE; to_fixed = (op == '1'); unsigned = (U == '1'); size = if sx == '0' then 16 else 32; frac_bits = size  UInt(imm4:i); case sf of when '01' fp_size = 16; d = UInt(Vd:D); when '10' fp_size = 32; d = UInt(Vd:D); when '11' fp_size = 64; d = UInt(D:Vd); if frac_bits < 0 then UNPREDICTABLE;
CONSTRAINED UNPREDICTABLE behavior
If frac_bits < 0, then one of the following behaviors must occur:
 The instruction is undefined.
 The instruction executes as NOP.
 The value in the destination register is unknown.
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly VCVT (between floatingpoint and fixedpoint).
Assembler Symbols
<c> 
<q> 
<dt> 
Is the data type for the fixedpoint number,
encoded in
U:sx:

<Sdm> 
Is the 32bit name of the SIMD&FP destination and source register, encoded in the "Vd:D" field. 
<Ddm> 
Is the 64bit name of the SIMD&FP destination and source register, encoded in the "D:Vd" field. 
Operation
if ConditionPassed() then EncodingSpecificOperations(); CheckVFPEnabled(TRUE); if to_fixed then bits(size) result; case fp_size of when 16 result = FPToFixed(S[d]<15:0>, frac_bits, unsigned, FPSCR, FPRounding_ZERO); S[d] = Extend(result, 32, unsigned); when 32 result = FPToFixed(S[d], frac_bits, unsigned, FPSCR, FPRounding_ZERO); S[d] = Extend(result, 32, unsigned); when 64 result = FPToFixed(D[d], frac_bits, unsigned, FPSCR, FPRounding_ZERO); D[d] = Extend(result, 64, unsigned); else case fp_size of when 16 bits(16) fp16 = FixedToFP(S[d]<size1:0>, frac_bits, unsigned, FPSCR, FPRounding_TIEEVEN); S[d] = Zeros(16):fp16; when 32 S[d] = FixedToFP(S[d]<size1:0>, frac_bits, unsigned, FPSCR, FPRounding_TIEEVEN); when 64 D[d] = FixedToFP(D[d]<size1:0>, frac_bits, unsigned, FPSCR, FPRounding_TIEEVEN);