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## CLZ

Count Leading Zeros returns the number of binary zero bits before the first binary one bit in a value.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

### A1

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 != 1111 0 0 0 1 0 1 1 0 (1) (1) (1) (1) Rd (1) (1) (1) (1) 0 0 0 1 Rm cond

#### A1

CLZ{<c>}{<q>} <Rd>, <Rm>

```d = UInt(Rd);  m = UInt(Rm);
if d == 15 || m == 15 then UNPREDICTABLE;```

### T1

 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 0 1 0 1 0 1 1 Rn 1 1 1 1 Rd 1 0 0 0 Rm

#### T1

CLZ{<c>}{<q>} <Rd>, <Rm>

```d = UInt(Rd);  m = UInt(Rm);  n = UInt(Rn);
if m != n || d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13```

### CONSTRAINED UNPREDICTABLE behavior

If m != n, then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction executes as described, with no change to its behavior and no additional side effects.
• The instruction executes with the additional decode: m = UInt(Rn);.
• The value in the destination register is unknown.

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

### Assembler Symbols



 Is the general-purpose destination register, encoded in the "Rd" field.
 For encoding A1: is the general-purpose source register, encoded in the "Rm" field. For encoding T1: is the general-purpose source register, encoded in the "Rm" field. It must be encoded with an identical value in the "Rn" field.

### Operation

```if ConditionPassed() then
EncodingSpecificOperations();