LDRD (literal)
Load Register Dual (literal) calculates an address from the PC value and an immediate offset, loads two words from memory, and writes them to two registers. For information about memory accesses see Memory accesses.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
A1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 0 | 0 | 0 | (1) | U | 1 | (0) | 0 | 1 | 1 | 1 | 1 | Rt | imm4H | 1 | 1 | 0 | 1 | imm4L | ||||||||||||
cond |
A1
LDRD{<c>}{<q>} <Rt>, <Rt2>, <label> // (Normal form)
LDRD{<c>}{<q>} <Rt>, <Rt2>, [PC, #{+/-}<imm>] // (Alternative form)
if Rt<0> == '1' then UNPREDICTABLE; t = UInt(Rt); t2 = t+1; imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == '1'); if t2 == 15 then UNPREDICTABLE;
CONSTRAINED UNPREDICTABLE behavior
If Rt<0> == '1', then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The instruction executes with the additional decode: t<0> = '0';.
- The instruction executes with the additional decode: t2 = t;.
- The instruction executes as described, with no change to its behavior and no additional side-effects. This does not apply when Rt == '1111'.
If P == '0' || W == '1', then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The instruction executes as if P == 1 and W == 0.'
T1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 0 | 0 | P | U | 1 | W | 1 | 1 | 1 | 1 | 1 | Rt | Rt2 | imm8 |
T1 (!(P == 0 && W == 0))
LDRD{<c>}{<q>} <Rt>, <Rt2>, <label> // (Normal form)
LDRD{<c>}{<q>} <Rt>, <Rt2>, [PC, #{+/-}<imm>] // (Alternative form)
if P == '0' && W == '0' then SEE "Related encodings"; t = UInt(Rt); t2 = UInt(Rt2); imm32 = ZeroExtend(imm8:'00', 32); add = (U == '1'); if t == 15 || t2 == 15 || t == t2 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13 if W == '1' then UNPREDICTABLE;
CONSTRAINED UNPREDICTABLE behavior
If t == t2, then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The load instruction executes but the destination register takes an unknown value.
If W == '1', then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The instruction executes without writeback of the base address.
- The instruction uses post-indexed addressing when P == '0' and uses pre-indexed addressing otherwise. The instruction is handled as described in Using R15.
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
Related encodings: Load/Store dual, Load/Store-Exclusive, Load-Acquire/Store-Release, table branch.
Assembler Symbols
<c> |
<q> |
+/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U:
|
The alternative syntax permits the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see Use of labels in UAL instruction syntax.
Operation
if ConditionPassed() then EncodingSpecificOperations(); address = if add then (Align(PC,4) + imm32) else (Align(PC,4) - imm32); if address == Align(address, 8) then data = MemA[address,8]; if BigEndian() then R[t] = data<63:32>; R[t2] = data<31:0>; else R[t] = data<31:0>; R[t2] = data<63:32>; else R[t] = MemA[address,4]; R[t2] = MemA[address+4,4];
Operational information
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.