LDRSH (immediate)
Load Register Signed Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) .
A1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 0 | 0 | 0 | P | U | 1 | W | 1 | != 1111 | Rt | imm4H | 1 | 1 | 1 | 1 | imm4L | |||||||||||||||
cond | Rn |
if Rn == '1111' then SEE "LDRSH (literal)"; if P == '0' && W == '1' then SEE "LDRSHT"; t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32); index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); if t == 15 || (wback && n == t) then UNPREDICTABLE;
CONSTRAINED UNPREDICTABLE behavior
If wback && n == t, then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is unknown. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.
T1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | != 1111 | != 1111 | imm12 | |||||||||||||||||
Rn | Rt |
if Rn == '1111' then SEE "LDRSH (literal)"; if Rt == '1111' then SEE "Related instructions"; t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32); index = TRUE; add = TRUE; wback = FALSE; // Armv8-A removes UNPREDICTABLE for R13
T2
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | != 1111 | Rt | 1 | P | U | W | imm8 | |||||||||||||
Rn |
if Rn == '1111' then SEE "LDRSH (literal)"; if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE "Related instructions"; if P == '1' && U == '1' && W == '0' then SEE "LDRSHT"; if P == '0' && W == '0' then UNDEFINED; t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32); index = (P == '1'); add = (U == '1'); wback = (W == '1'); if (t == 15 && W == '1') || (wback && n == t) then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13
CONSTRAINED UNPREDICTABLE behavior
If wback && n == t, then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is unknown. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
Related instructions: Load/store single.
Assembler Symbols
<c> |
<q> |
<Rt> |
Is the general-purpose register to be transferred, encoded in the "Rt" field. |
<Rn> |
Is the general-purpose base register, encoded in the "Rn" field. For PC use see LDRSH (literal). |
+/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U:
|
+ |
Specifies the offset is added to the base register. |
Operation
if ConditionPassed() then EncodingSpecificOperations(); offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); address = if index then offset_addr else R[n]; data = MemU[address,2]; if wback then R[n] = offset_addr; R[t] = SignExtend(data, 32);
Operational information
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.