STR (register)
Store Register (register) calculates an address from a base register value and an offset register value, stores a word from a register to memory. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) .
A1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 0 | 1 | 1 | P | U | 0 | W | 0 | Rn | Rt | imm5 | stype | 0 | Rm | |||||||||||||||||
cond |
if P == '0' && W == '1' then SEE "STRT"; t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); (shift_t, shift_n) = DecodeImmShift(stype, imm5); if m == 15 then UNPREDICTABLE; if wback && (n == 15 || n == t) then UNPREDICTABLE;
CONSTRAINED UNPREDICTABLE behavior
If wback && n == t, then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The store instruction executes but the value stored is unknown.
If wback && n == 15, then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The instruction executes without writeback of the base address.
- The instruction uses the addressing mode described in the equivalent immediate offset instruction.
T1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 0 | 1 | 0 | 0 | 0 | Rm | Rn | Rt |
t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); index = TRUE; add = TRUE; wback = FALSE; (shift_t, shift_n) = (SRType_LSL, 0);
T2
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | != 1111 | Rt | 0 | 0 | 0 | 0 | 0 | 0 | imm2 | Rm | ||||||||||
Rn |
if Rn == '1111' then UNDEFINED; t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); index = TRUE; add = TRUE; wback = FALSE; (shift_t, shift_n) = (SRType_LSL, UInt(imm2)); if t == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13
CONSTRAINED UNPREDICTABLE behavior
If t == 15, then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is unknown.
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
Assembler Symbols
<c> |
<q> |
+/- |
Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U:
|
+ |
Specifies the index register is added to the base register. |
<Rm> |
Is the general-purpose index register, encoded in the "Rm" field. |
<shift> |
The shift to apply to the value read from <Rm>. If absent, no shift is applied. Otherwise, see Shifts applied to a register. |
<imm> |
If present, the size of the left shift to apply to the value from <Rm>, in the range 1-3. <imm> is encoded in imm2. If absent, no shift is specified and imm2 is encoded as 0b00. |
Operation
if ConditionPassed() then EncodingSpecificOperations(); offset = Shift(R[m], shift_t, shift_n, PSTATE.C); offset_addr = if add then (R[n] + offset) else (R[n] - offset); address = if index then offset_addr else R[n]; if t == 15 then // Only possible for encoding A1 data = PCStoreValue(); else data = R[t]; MemU[address,4] = data; if wback then R[n] = offset_addr;
Operational information
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.