TEQ (register-shifted register)
Test Equivalence (register-shifted register) performs a bitwise exclusive OR operation on a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result.
A1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | Rn | (0) | (0) | (0) | (0) | Rs | 0 | stype | 1 | Rm | |||||||||||||
cond |
n = UInt(Rn); m = UInt(Rm); s = UInt(Rs); shift_t = DecodeRegShift(stype); if n == 15 || m == 15 || s == 15 then UNPREDICTABLE;
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
Assembler Symbols
<c> |
<q> |
<Rn> |
Is the first general-purpose source register, encoded in the "Rn" field. |
<Rm> |
Is the second general-purpose source register, encoded in the "Rm" field. |
<type> |
Is the type of shift to be applied to the second source register,
encoded in
stype:
|
<Rs> |
Is the third general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field. |
Operation
if ConditionPassed() then EncodingSpecificOperations(); shift_n = UInt(R[s]<7:0>); (shifted, carry) = Shift_C(R[m], shift_t, shift_n, PSTATE.C); result = R[n] EOR shifted; PSTATE.N = result<31>; PSTATE.Z = IsZeroBit(result); PSTATE.C = carry; // PSTATE.V unchanged
Operational information
If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:
- The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.