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VCVT (floating-point to integer, floating-point)

Convert floating-point to integer with Round towards Zero converts a value in a register from floating-point to a 32-bit integer, using the Round towards Zero rounding mode, and places the result in a second register.

VCVT (between floating-point and fixed-point, floating-point) describes conversions between floating-point and 16-bit integers.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 != 1111 1 1 1 0 1 D 1 1 1 1 0 x Vd 1 0 size 1 1 M 0 Vm cond opc2 op

Half-precision scalar (opc2 == 100 && size == 01)(Armv8.2)

VCVT{<c>}{<q>}.U32.F16 <Sd>, <Sm>

Half-precision scalar (opc2 == 101 && size == 01)(Armv8.2)

VCVT{<c>}{<q>}.S32.F16 <Sd>, <Sm>

Single-precision scalar (opc2 == 100 && size == 10)

VCVT{<c>}{<q>}.U32.F32 <Sd>, <Sm>

Single-precision scalar (opc2 == 101 && size == 10)

VCVT{<c>}{<q>}.S32.F32 <Sd>, <Sm>

Double-precision scalar (opc2 == 100 && size == 11)

VCVT{<c>}{<q>}.U32.F64 <Sd>, <Dm>

Double-precision scalar (opc2 == 101 && size == 11)

VCVT{<c>}{<q>}.S32.F64 <Sd>, <Dm>

```if opc2 != '000' && opc2 != '10x' then SEE "Related encodings";
if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED;
if size == '01' && cond != '1110' then UNPREDICTABLE;
to_integer = (opc2<2> == '1');
if to_integer then
unsigned = (opc2<0> == '0');
rounding = if op == '1' then FPRounding_ZERO else FPRoundingMode(FPSCR);
d = UInt(Vd:D);
case size of
when '01' esize = 16; m = UInt(Vm:M);
when '10' esize = 32; m = UInt(Vm:M);
when '11' esize = 64; m = UInt(M:Vm);
else
unsigned = (op == '0');
rounding = FPRoundingMode(FPSCR);
m = UInt(Vm:M);
case size of
when '01' esize = 16; d = UInt(Vd:D);
when '10' esize = 32; d = UInt(Vd:D);
when '11' esize = 64; d = UInt(D:Vd);```

CONSTRAINED UNPREDICTABLE behavior

If size == '01' && cond != '1110', then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as if it passes the Condition code check.
• The instruction executes as NOP. This means it behaves as if it fails the Condition code check.

T1

 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 0 1 1 1 0 1 D 1 1 1 1 0 x Vd 1 0 size 1 1 M 0 Vm opc2 op

Half-precision scalar (opc2 == 100 && size == 01)(Armv8.2)

VCVT{<c>}{<q>}.U32.F16 <Sd>, <Sm>

Half-precision scalar (opc2 == 101 && size == 01)(Armv8.2)

VCVT{<c>}{<q>}.S32.F16 <Sd>, <Sm>

Single-precision scalar (opc2 == 100 && size == 10)

VCVT{<c>}{<q>}.U32.F32 <Sd>, <Sm>

Single-precision scalar (opc2 == 101 && size == 10)

VCVT{<c>}{<q>}.S32.F32 <Sd>, <Sm>

Double-precision scalar (opc2 == 100 && size == 11)

VCVT{<c>}{<q>}.U32.F64 <Sd>, <Dm>

Double-precision scalar (opc2 == 101 && size == 11)

VCVT{<c>}{<q>}.S32.F64 <Sd>, <Dm>

```if opc2 != '000' && opc2 != '10x' then SEE "Related encodings";
if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED;
if size == '01' && InITBlock()  then UNPREDICTABLE;
to_integer = (opc2<2> == '1');
if to_integer then
unsigned = (opc2<0> == '0');
rounding = if op == '1' then FPRounding_ZERO else FPRoundingMode(FPSCR);
d = UInt(Vd:D);
case size of
when '01' esize = 16; m = UInt(Vm:M);
when '10' esize = 32; m = UInt(Vm:M);
when '11' esize = 64; m = UInt(M:Vm);
else
unsigned = (op == '0');
rounding = FPRoundingMode(FPSCR);
m = UInt(Vm:M);
case size of
when '01' esize = 16; d = UInt(Vd:D);
when '10' esize = 32; d = UInt(Vd:D);
when '11' esize = 64; d = UInt(D:Vd);```

CONSTRAINED UNPREDICTABLE behavior

If size == '01' && InITBlock(), then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as if it passes the Condition code check.
• The instruction executes as NOP. This means it behaves as if it fails the Condition code check.

Related encodings: See Floating-point data-processing for the T32 instruction set, or Floating-point data-processing for the A32 instruction set.

Assembler Symbols



 Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.
 Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field.
 Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

Operation

```if ConditionPassed() then
EncodingSpecificOperations();  CheckVFPEnabled(TRUE);
if to_integer then
case esize of
when 16
S[d] = FPToFixed(S[m]<15:0>, 0, unsigned, FPSCR, rounding);
when 32
S[d] = FPToFixed(S[m], 0, unsigned, FPSCR, rounding);
when 64
S[d] = FPToFixed(D[m], 0, unsigned, FPSCR, rounding);
else
case esize of
when 16
bits(16) fp16 = FixedToFP(S[m], 0, unsigned, FPSCR, rounding);
S[d] = Zeros(16):fp16;
when 32
S[d] = FixedToFP(S[m], 0, unsigned, FPSCR, rounding);
when 64
D[d] = FixedToFP(S[m], 0, unsigned, FPSCR, rounding);```