You copied the Doc URL to your clipboard.

VMOV (between two general-purpose registers and two single-precision registers)

Copy two general-purpose registers to a pair of 32-bit SIMD&FP registers transfers the contents of two consecutively numbered single-precision Floating-point registers to two general-purpose registers, or the contents of two general-purpose registers to a pair of single-precision Floating-point registers. The general-purpose registers do not have to be contiguous.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 11111100010opRt2Rt101000M1Vm
cond

From general-purpose registers (op == 0)

VMOV{<c>}{<q>} <Sm>, <Sm1>, <Rt>, <Rt2>

To general-purpose registers (op == 1)

VMOV{<c>}{<q>} <Rt>, <Rt2>, <Sm>, <Sm1>

to_arm_registers = (op == '1');  t = UInt(Rt);  t2 = UInt(Rt2);  m = UInt(Vm:M);
if t == 15 || t2 == 15 || m == 31 then UNPREDICTABLE;
if to_arm_registers && t == t2 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If to_arm_registers && t == t2, then one of the following behaviors must occur:

  • The instruction is undefined.
  • The instruction executes as NOP.
  • The value in the destination register is unknown.

If m == 31, then one of the following behaviors must occur:

  • The instruction is undefined.
  • The instruction executes as NOP.
  • One or more of the single-precision registers become unknown for a move to the single-precision register. The general-purpose registers listed in the instruction become unknown for a move from the single-precision registers. This behavior does not affect any other general-purpose registers.

T1

15141312111098765432101514131211109876543210
11101100010opRt2Rt101000M1Vm

From general-purpose registers (op == 0)

VMOV{<c>}{<q>} <Sm>, <Sm1>, <Rt>, <Rt2>

To general-purpose registers (op == 1)

VMOV{<c>}{<q>} <Rt>, <Rt2>, <Sm>, <Sm1>

to_arm_registers = (op == '1');  t = UInt(Rt);  t2 = UInt(Rt2);  m = UInt(Vm:M);
if t == 15 || t2 == 15 || m == 31 then UNPREDICTABLE;
if to_arm_registers && t == t2 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If to_arm_registers && t == t2, then one of the following behaviors must occur:

  • The instruction is undefined.
  • The instruction executes as NOP.
  • The value in the destination register is unknown.

If m == 31, then one of the following behaviors must occur:

  • The instruction is undefined.
  • The instruction executes as NOP.
  • One or more of the single-precision registers become unknown for a move to the single-precision register. The general-purpose registers listed in the instruction become unknown for a move from the single-precision registers. This behavior does not affect any other general-purpose registers.

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly VMOV (between two general-purpose registers and two single-precision registers).

Assembler Symbols

<Rt2>

Is the second general-purpose register that <Sm1> will be transferred to or from, encoded in the "Rt2" field.

<Rt>

Is the first general-purpose register that <Sm> will be transferred to or from, encoded in the "Rt" field.

<Sm1>

Is the 32-bit name of the second SIMD&FP register to be transferred. This is the next SIMD&FP register after <Sm>.

<Sm>

Is the 32-bit name of the first SIMD&FP register to be transferred, encoded in the "Vm:M" field.

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckVFPEnabled(TRUE);
    if to_arm_registers then
        R[t] = S[m];
        R[t2] = S[m+1];
    else
        S[m] = R[t];
        S[m+1] = R[t2];

Operational information

If CPSR.DIT is 1 and this instruction passes its condition execution check:

  • The execution time of this instruction is independent of:
    • The values of the data supplied in any of its registers.
    • The values of the NZCV flags.
  • The response of this instruction to asynchronous exceptions does not vary based on:
    • The values of the data supplied in any of its registers.
    • The values of the NZCV flags.
Was this page helpful? Yes No