You copied the Doc URL to your clipboard.

VORN (immediate)

Vector Bitwise OR NOT (immediate) performs a bitwise OR between a register value and the complement of an immediate value, and returns the result into the destination vector.

This is a pseudo-instruction of VORR (immediate). This means:

  • The encodings in this description are named to match the encodings of VORR (immediate).
  • The assembler syntax is used only for assembly, and is not used on disassembly.
  • The description of VORR (immediate) gives the operational pseudocode for this instruction.

It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 and T2 ) .

A1

313029282726252423222120191817161514131211109876543210
1111001i1D000imm3Vd0xx10Q01imm4
cmode

64-bit SIMD vector (Q == 0)

VORN{<c>}{<q>}.I16 {<Dd>,} <Dd>, #<imm>

is equivalent to

VORR{<c>}{<q>}.I16 <Dd>, #~<imm>

128-bit SIMD vector (Q == 1)

VORN{<c>}{<q>}.I16 {<Qd>,} <Qd>, #<imm>

is equivalent to

VORR{<c>}{<q>}.I16 <Qd>, #~<imm>

A2

313029282726252423222120191817161514131211109876543210
1111001i1D000imm3Vd10x10Q01imm4
cmode

64-bit SIMD vector (Q == 0)

VORN{<c>}{<q>}.I32 {<Dd>,} <Dd>, #<imm>

is equivalent to

VORR{<c>}{<q>}.I32 <Dd>, #~<imm>

128-bit SIMD vector (Q == 1)

VORN{<c>}{<q>}.I32 {<Qd>,} <Qd>, #<imm>

is equivalent to

VORR{<c>}{<q>}.I32 <Qd>, #~<imm>

T1

15141312111098765432101514131211109876543210
111i11111D000imm3Vd0xx10Q01imm4
cmode

64-bit SIMD vector (Q == 0)

VORN{<c>}{<q>}.I16 {<Dd>,} <Dd>, #<imm>

is equivalent to

VORR{<c>}{<q>}.I16 <Dd>, #~<imm>

128-bit SIMD vector (Q == 1)

VORN{<c>}{<q>}.I16 {<Qd>,} <Qd>, #<imm>

is equivalent to

VORR{<c>}{<q>}.I16 <Qd>, #~<imm>

T2

15141312111098765432101514131211109876543210
111i11111D000imm3Vd10x10Q01imm4
cmode

64-bit SIMD vector (Q == 0)

VORN{<c>}{<q>}.I32 {<Dd>,} <Dd>, #<imm>

is equivalent to

VORR{<c>}{<q>}.I32 <Dd>, #~<imm>

128-bit SIMD vector (Q == 1)

VORN{<c>}{<q>}.I32 {<Qd>,} <Qd>, #<imm>

is equivalent to

VORR{<c>}{<q>}.I32 <Qd>, #~<imm>

Assembler Symbols

<c>

For encoding A1 and A2: see Standard assembler syntax fields. This encoding must be unconditional.

For encoding T1 and T2: see Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Qd>

Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<imm>

Is a constant of the specified type that is replicated to fill the destination register. For details of the range of constants available and the encoding of <imm>, see Modified immediate constants in T32 and A32 Advanced SIMD instructions.

Operation

The description of VORR (immediate) gives the operational pseudocode for this instruction.

Was this page helpful? Yes No