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## VMINNM

This instruction determines the floating point minimum number.

It handles NaNs in consistence with the IEEE754-2008 specification. It returns the numerical operand when one operand is numerical and the other is a quiet NaN, but otherwise the result is identical to floating-point VMIN.

This instruction is not conditional.

It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 and T2 ) .

### A1

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 0 0 1 1 0 D 1 sz Vn Vd 1 1 1 1 N Q M 1 Vm op

#### 64-bit SIMD vector (Q == 0)

VMINNM{<q>}.<dt> <Dd>, <Dn>, <Dm>

#### 128-bit SIMD vector (Q == 1)

VMINNM{<q>}.<dt> <Qd>, <Qn>, <Qm>

```if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
if sz == '1' && !HaveFP16Ext() then UNDEFINED;
maximum = (op == '0');
case sz of
when '0' esize = 32; elements = 2;
when '1' esize = 16; elements = 4;
d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); regs = if Q == '0' then 1 else 2;```

### A2

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 0 1 D 0 0 Vn Vd 1 0 != 00 N 1 M 0 Vm size op

#### Half-precision scalar (size == 01)(Armv8.2)

VMINNM{<q>}.F16 <Sd>, <Sn>, <Sm> // (Cannot be conditional)

#### Single-precision scalar (size == 10)

VMINNM{<q>}.F32 <Sd>, <Sn>, <Sm> // (Cannot be conditional)

#### Double-precision scalar (size == 11)

VMINNM{<q>}.F64 <Dd>, <Dn>, <Dm> // (Cannot be conditional)

```if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED;
maximum = (op == '0');
case size of
when '01' esize = 16; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M);
when '10' esize = 32; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M);
when '11' esize = 64; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm);```

### T1

 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 0 D 1 sz Vn Vd 1 1 1 1 N Q M 1 Vm op

#### 64-bit SIMD vector (Q == 0)

VMINNM{<q>}.<dt> <Dd>, <Dn>, <Dm>

#### 128-bit SIMD vector (Q == 1)

VMINNM{<q>}.<dt> <Qd>, <Qn>, <Qm>

```if InITBlock() then UNPREDICTABLE;
if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
if sz == '1' && !HaveFP16Ext() then UNDEFINED;
maximum = (op == '0');
case sz of
when '0' esize = 32; elements = 2;
when '1' esize = 16; elements = 4;
d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); regs = if Q == '0' then 1 else 2;```

### CONSTRAINED UNPREDICTABLE behavior

If InITBlock(), then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as if it passes the Condition code check.
• The instruction executes as NOP. This means it behaves as if it fails the Condition code check.

### T2

 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 0 1 D 0 0 Vn Vd 1 0 != 00 N 1 M 0 Vm size op

#### Half-precision scalar (size == 01)(Armv8.2)

VMINNM{<q>}.F16 <Sd>, <Sn>, <Sm> // (Not permitted in IT block)

#### Single-precision scalar (size == 10)

VMINNM{<q>}.F32 <Sd>, <Sn>, <Sm> // (Not permitted in IT block)

#### Double-precision scalar (size == 11)

VMINNM{<q>}.F64 <Dd>, <Dn>, <Dm> // (Not permitted in IT block)

```if InITBlock() then UNPREDICTABLE;
if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED;
maximum = (op == '0');
case size of
when '01' esize = 16; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M);
when '10' esize = 32; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M);
when '11' esize = 64; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm);```

### CONSTRAINED UNPREDICTABLE behavior

If InITBlock(), then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as if it passes the Condition code check.
• The instruction executes as NOP. This means it behaves as if it fails the Condition code check.

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

### Assembler Symbols


<dt> Is the data type for the elements of the vectors, encoded in sz:
sz <dt>
0 F32
1 F16
 Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as *2.
 Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as *2.
 Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as *2.

Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
 Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
 Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
 Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.
 Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.
 Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.

### Operation

```EncodingSpecificOperations();  CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
for r = 0 to regs-1
for e = 0 to elements-1
op1 = Elem[D[n+r], e, esize]; op2 = Elem[D[m+r], e, esize];
if maximum then
Elem[D[d+r], e, esize] = FPMaxNum(op1, op2, StandardFPSCRValue());
else
Elem[D[d+r], e, esize] = FPMinNum(op1, op2, StandardFPSCRValue());
else                        // VFP instruction
case esize of
when 16
if maximum then
S[d] = Zeros(16) : FPMaxNum(S[n]<15:0>, S[m]<15:0>, FPSCR);
else
S[d] = Zeros(16) : FPMinNum(S[n]<15:0>, S[m]<15:0>, FPSCR);
when 32
if maximum then
S[d] = FPMaxNum(S[n], S[m], FPSCR);
else
S[d] = FPMinNum(S[n], S[m], FPSCR);
when 64
if maximum then
D[d] = FPMaxNum(D[n], D[m], FPSCR);
else
D[d] = FPMinNum(D[n], D[m], FPSCR);```