Arm® A32/T32 Instruction Set Architecture: Armv8, for Armv8-A architecture profile Documentation

PSSBB

Physical Speculative Store Bypass Barrier is a memory barrier which prevents speculative loads from bypassing earlier stores to the same physical address.

The semantics of the Physical Speculative Store Bypass Barrier are:

• When a load to a location appears in program order after the PSSBB, then the load does not speculatively read an entry earlier in the coherence order for that location than the entry generated by the latest store satisfying all of the following conditions:
  • The store is to the same location as the load.
  • The store appears in program order before the PSSBB.
• When a load to a location appears in program order before the PSSBB, then the load does not speculatively read data from any store satisfying all of the following conditions:
  • The store is to the same location as the load.
  • The store appears in program order after the PSSBB.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

// No additional decoding required

T1

if InITBlock() then UNPREDICTABLE;

Assembler Symbols

if ConditionPassed() then
    EncodingSpecificOperations();
    SpeculativeStoreBypassBarrierToPA();