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## SMMUL, SMMULR

Signed Most Significant Word Multiply multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and writes those bits to the destination register.

Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the product before the high word is extracted.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

### A1

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 != 1111 0 1 1 1 0 1 0 1 Rd 1 1 1 1 Rm 0 0 R 1 Rn cond

#### SMMUL (R == 0)

SMMUL{<c>}{<q>} {<Rd>,} <Rn>, <Rm>

#### SMMULR (R == 1)

SMMULR{<c>}{<q>} {<Rd>,} <Rn>, <Rm>

```d = UInt(Rd);  n = UInt(Rn);  m = UInt(Rm);  round = (R == '1');
if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;```

### T1

 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 0 1 1 0 1 0 1 Rn 1 1 1 1 Rd 0 0 0 R Rm

#### SMMUL (R == 0)

SMMUL{<c>}{<q>} {<Rd>,} <Rn>, <Rm>

#### SMMULR (R == 1)

SMMULR{<c>}{<q>} {<Rd>,} <Rn>, <Rm>

```d = UInt(Rd);  n = UInt(Rn);  m = UInt(Rm);  round = (R == '1');
if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13```

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

### Assembler Symbols



 Is the general-purpose destination register, encoded in the "Rd" field.
 Is the first general-purpose source register, encoded in the "Rn" field.
 Is the second general-purpose source register, encoded in the "Rm" field.

### Operation

```if ConditionPassed() then
EncodingSpecificOperations();
result = SInt(R[n]) * SInt(R[m]);
if round then result = result + 0x80000000;
R[d] = result<63:32>;```

### Operational information

If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:

• The execution time of this instruction is independent of:
• The values of the data supplied in any of its registers.
• The values of the NZCV flags.
• The response of this instruction to asynchronous exceptions does not vary based on:
• The values of the data supplied in any of its registers.
• The values of the NZCV flags.