STRD (immediate)
Store Register Dual (immediate) calculates an address from a base register value and an immediate offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
A1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 0 | 0 | 0 | P | U | 1 | W | 0 | Rn | Rt | imm4H | 1 | 1 | 1 | 1 | imm4L | |||||||||||||||
cond |
if Rt<0> == '1' then UNPREDICTABLE; t = UInt(Rt); t2 = t+1; n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32); index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); if P == '0' && W == '1' then UNPREDICTABLE; if wback && (n == 15 || n == t || n == t2) then UNPREDICTABLE; if t2 == 15 then UNPREDICTABLE;
CONSTRAINED UNPREDICTABLE behavior
If t == 15 || t2 == 15, then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is unknown.
If wback && (n == t || n == t2), then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The store instruction executes but the value stored is unknown.
If wback && n == 15, then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The instruction executes without writeback of the base address.
- The instruction uses the addressing mode described in the equivalent immediate offset instruction.
If Rt<0> == '1', then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The instruction executes with the additional decode: t<0> = '0'.
- The instruction executes with the additional decode: t2 = t.
- The instruction executes as described, with no change to its behavior and no additional side-effects. This does not apply when Rt == '1111'.
If P == '0' && W == '1', then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The instruction executes as an LDRD using one of offset, post-indexed, or pre-indexed addressing.
T1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 0 | 0 | P | U | 1 | W | 0 | != 1111 | Rt | Rt2 | imm8 | ||||||||||||||||
Rn |
if P == '0' && W == '0' then SEE "Related encodings"; t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); imm32 = ZeroExtend(imm8:'00', 32); index = (P == '1'); add = (U == '1'); wback = (W == '1'); if wback && (n == t || n == t2) then UNPREDICTABLE; if n == 15 || t == 15 || t2 == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13
CONSTRAINED UNPREDICTABLE behavior
If t == 15 || t2 == 15, then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is unknown.
If wback && (n == t || n == t2), then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The store instruction executes but the value stored is unknown.
If wback && n == 15, then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as NOP.
- The instruction executes without writeback of the base address.
- The instruction uses the addressing mode described in the equivalent immediate offset instruction.
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
Related encodings: Load/store dual, load/store exclusive, table branch.
Assembler Symbols
<c> |
<q> |
+/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U:
|
Operation
if ConditionPassed() then EncodingSpecificOperations(); offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); address = if index then offset_addr else R[n]; if address == Align(address, 8) then bits(64) data; if BigEndian() then data<63:32> = R[t]; data<31:0> = R[t2]; else data<31:0> = R[t]; data<63:32> = R[t2]; MemA[address,8] = data; else MemA[address,4] = R[t]; MemA[address+4,4] = R[t2]; if wback then R[n] = offset_addr;
Operational information
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.