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UDF
Permanently Undefined generates an Undefined Instruction exception.
The encodings for UDF used in this section are defined as permanently undefined in the Armv8-A architecture. However:
- With the T32 instruction set, Arm deprecates using the UDF instruction in an IT block.
- In the A32 instruction set, UDF is not conditional.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) .
A1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | imm12 | 1 | 1 | 1 | 1 | imm4 | ||||||||||||||
cond |
imm32 = ZeroExtend(imm12:imm4, 32); // imm32 is for assembly and disassembly only, and is ignored by hardware.
T1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | imm8 |
imm32 = ZeroExtend(imm8, 32); // imm32 is for assembly and disassembly only, and is ignored by hardware.
T2
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | imm4 | 1 | 0 | 1 | 0 | imm12 |
imm32 = ZeroExtend(imm4:imm12, 32); // imm32 is for assembly and disassembly only, and is ignored by hardware.
Assembler Symbols
<c> |
For encoding A1: see Standard assembler syntax fields. <c> must be AL or omitted. |
For encoding T1 and T2: see Standard assembler syntax fields. Arm deprecates using any <c> value other than AL. |
<q> |