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## UDIV

Unsigned Divide divides a 32-bit unsigned integer register value by a 32-bit unsigned integer register value, and writes the result to the destination register. The condition flags are not affected.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

### A1

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 != 1111 0 1 1 1 0 0 1 1 Rd (1) (1) (1) (1) Rm 0 0 0 1 Rn cond Ra

#### A1

UDIV{<c>}{<q>} {<Rd>,} <Rn>, <Rm>

```d = UInt(Rd);  n = UInt(Rn);  m = UInt(Rm);  a = UInt(Ra);
if d == 15 || n == 15 || m == 15 || a != 15 then UNPREDICTABLE;```

### CONSTRAINED UNPREDICTABLE behavior

If Ra != '1111', then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction executes as described, with no change to its behavior and no additional side effects.
• The instruction performs a divide and the register specified by Ra becomes unknown.

### T1

 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 0 1 1 1 0 1 1 Rn (1) (1) (1) (1) Rd 1 1 1 1 Rm Ra

#### T1

UDIV{<c>}{<q>} {<Rd>,} <Rn>, <Rm>

```d = UInt(Rd);  n = UInt(Rn);  m = UInt(Rm);  a = UInt(Ra);
if d == 15 || n == 15 || m == 15 || a != 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13```

### CONSTRAINED UNPREDICTABLE behavior

If Ra != '1111', then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction executes as described, with no change to its behavior and no additional side effects.
• The instruction performs a divide and the register specified by Ra becomes unknown.

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

### Assembler Symbols



 Is the general-purpose destination register, encoded in the "Rd" field.
 Is the first general-purpose source register holding the dividend, encoded in the "Rn" field.
 Is the second general-purpose source register holding the divisor, encoded in the "Rm" field.

### Operation

```if ConditionPassed() then
EncodingSpecificOperations();
if UInt(R[m]) == 0 then
result = 0;
else
result = RoundTowardsZero(Real(UInt(R[n])) / Real(UInt(R[m])));
R[d] = result<31:0>;```