VCVT (integer to floating-point, floating-point)
Convert integer to floating-point converts a 32-bit integer to floating-point using the rounding mode specified by the FPSCR, and places the result in a second register.
VCVT (between floating-point and fixed-point, floating-point) describes conversions between floating-point and 16-bit integers.
Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
A1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | 1 | 0 | 0 | 0 | Vd | 1 | 0 | size | op | 1 | M | 0 | Vm | ||||||||||
cond | opc2 |
if opc2 != '000' && opc2 != '10x' then SEE "Related encodings"; if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED; if size == '01' && cond != '1110' then UNPREDICTABLE; to_integer = (opc2<2> == '1'); if to_integer then unsigned = (opc2<0> == '0'); rounding = if op == '1' then FPRounding_ZERO else FPRoundingMode(FPSCR); d = UInt(Vd:D); case size of when '01' esize = 16; m = UInt(Vm:M); when '10' esize = 32; m = UInt(Vm:M); when '11' esize = 64; m = UInt(M:Vm); else unsigned = (op == '0'); rounding = FPRoundingMode(FPSCR); m = UInt(Vm:M); case size of when '01' esize = 16; d = UInt(Vd:D); when '10' esize = 32; d = UInt(Vd:D); when '11' esize = 64; d = UInt(D:Vd);
CONSTRAINED UNPREDICTABLE behavior
If size == '01' && cond != '1110', then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as if it passes the Condition code check.
- The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
T1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | 1 | 0 | 0 | 0 | Vd | 1 | 0 | size | op | 1 | M | 0 | Vm | |||||||
opc2 |
if opc2 != '000' && opc2 != '10x' then SEE "Related encodings"; if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED; if size == '01' && InITBlock() then UNPREDICTABLE; to_integer = (opc2<2> == '1'); if to_integer then unsigned = (opc2<0> == '0'); rounding = if op == '1' then FPRounding_ZERO else FPRoundingMode(FPSCR); d = UInt(Vd:D); case size of when '01' esize = 16; m = UInt(Vm:M); when '10' esize = 32; m = UInt(Vm:M); when '11' esize = 64; m = UInt(M:Vm); else unsigned = (op == '0'); rounding = FPRoundingMode(FPSCR); m = UInt(Vm:M); case size of when '01' esize = 16; d = UInt(Vd:D); when '10' esize = 32; d = UInt(Vd:D); when '11' esize = 64; d = UInt(D:Vd);
CONSTRAINED UNPREDICTABLE behavior
If size == '01' && InITBlock(), then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as if it passes the Condition code check.
- The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
Related encodings: See Floating-point data-processing for the T32 instruction set, or Floating-point data-processing for the A32 instruction set.
Assembler Symbols
<c> |
<q> |
<dt> |
Is the data type for the operand,
encoded in
op:
|
<Sd> |
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field. |
<Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
<Sm> |
Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field. |
Operation
if ConditionPassed() then EncodingSpecificOperations(); CheckVFPEnabled(TRUE); if to_integer then case esize of when 16 S[d] = FPToFixed(S[m]<15:0>, 0, unsigned, FPSCR, rounding); when 32 S[d] = FPToFixed(S[m], 0, unsigned, FPSCR, rounding); when 64 S[d] = FPToFixed(D[m], 0, unsigned, FPSCR, rounding); else case esize of when 16 bits(16) fp16 = FixedToFP(S[m], 0, unsigned, FPSCR, rounding); S[d] = Zeros(16):fp16; when 32 S[d] = FixedToFP(S[m], 0, unsigned, FPSCR, rounding); when 64 D[d] = FixedToFP(S[m], 0, unsigned, FPSCR, rounding);