VEXT (multibyte elements)
Vector Extract extracts elements from the bottom end of the second operand vector and the top end of the first, concatenates them and places the result in the destination vector.
This is a pseudo-instruction of VEXT (byte elements). This means:
- The encodings in this description are named to match the encodings of VEXT (byte elements).
- The assembler syntax is used only for assembly, and is not used on disassembly.
- The description of VEXT (byte elements) gives the operational pseudocode for this instruction.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
A1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | D | 1 | 1 | Vn | Vd | imm4 | N | Q | M | 0 | Vm |
T1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | D | 1 | 1 | Vn | Vd | imm4 | N | Q | M | 0 | Vm |
Assembler Symbols
<c> |
For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional. |
For encoding T1: see Standard assembler syntax fields. |
<q> |
<size> |
For the 64-bit SIMD vector variant: is the size of the operation, and can be one of 16 or 32. |
For the 128-bit SIMD vector variant: is the size of the operation, and can be one of 16, 32 or 64. |
<Qd> |
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. |
<Qn> |
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2. |
<Qm> |
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2. |
<Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
<Dn> |
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field. |
<Dm> |
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field. |
Operation
The description of VEXT (byte elements) gives the operational pseudocode for this instruction.