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## VRINTR

Round floating-point to integer rounds a floating-point value to an integral floating-point value of the same size using the rounding mode specified in the FPSCR. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

### A1

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 != 1111 1 1 1 0 1 D 1 1 0 1 1 0 Vd 1 0 size 0 1 M 0 Vm cond op

#### Half-precision scalar (size == 01)(Armv8.2)

VRINTR{<c>}{<q>}.F16 <Sd>, <Sm>

#### Single-precision scalar (size == 10)

VRINTR{<c>}{<q>}.F32 <Sd>, <Sm>

#### Double-precision scalar (size == 11)

VRINTR{<c>}{<q>}.F64 <Dd>, <Dm>

```if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED;
if size == '01' && cond != '1110' then UNPREDICTABLE;
rounding = if op == '1' then FPRounding_ZERO else FPRoundingMode(FPSCR);
exact = FALSE;
case size of
when '01' esize = 16; d = UInt(Vd:D); m = UInt(Vm:M);
when '10' esize = 32; d = UInt(Vd:D); m = UInt(Vm:M);
when '11' esize = 64; d = UInt(D:Vd); m = UInt(M:Vm);```

### T1

 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 0 1 1 1 0 1 D 1 1 0 1 1 0 Vd 1 0 size 0 1 M 0 Vm op

#### Half-precision scalar (size == 01)(Armv8.2)

VRINTR{<c>}{<q>}.F16 <Sd>, <Sm>

#### Single-precision scalar (size == 10)

VRINTR{<c>}{<q>}.F32 <Sd>, <Sm>

#### Double-precision scalar (size == 11)

VRINTR{<c>}{<q>}.F64 <Dd>, <Dm>

```if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED;
if size == '01' && InITBlock()  then UNPREDICTABLE;
rounding = if op == '1' then FPRounding_ZERO else FPRoundingMode(FPSCR);
exact = FALSE;
case size of
when '01' esize = 16; d = UInt(Vd:D); m = UInt(Vm:M);
when '10' esize = 32; d = UInt(Vd:D); m = UInt(Vm:M);
when '11' esize = 64; d = UInt(D:Vd); m = UInt(M:Vm);```

### CONSTRAINED UNPREDICTABLE behavior

If InITBlock(), then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as if it passes the Condition code check.
• The instruction executes as NOP. This means it behaves as if it fails the Condition code check.

### Assembler Symbols



 Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.
 Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field.

Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
 Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

### Operation

```if ConditionPassed() then
EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
case esize of
when 16
S[d] = Zeros(16) : FPRoundInt(S[m]<15:0>, FPSCR, rounding, exact);
when 32
S[d] = FPRoundInt(S[m], FPSCR, rounding, exact);
when 64
D[d] = FPRoundInt(D[m], FPSCR, rounding, exact);```