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VSHLL

Vector Shift Left Long takes each element in a doubleword vector, left shifts them by an immediate value, and places the results in a quadword vector.

The operand elements can be:

  • 8-bit, 16-bit, or 32-bit signed integers.
  • 8-bit, 16-bit, or 32-bit unsigned integers.
  • 8-bit, 16-bit, or 32-bit untyped integers, maximum shift only.

The result elements are twice the length of the operand elements.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 and T2 ) .

A1

313029282726252423222120191817161514131211109876543210
1111001U1Dimm6Vd101000M1Vm

A1 (imm6 != 000xxx)

VSHLL{<c>}{<q>}.<type><size> <Qd>, <Dm>, #<imm>

if imm6 == '000xxx' then SEE "Related encodings";
if Vd<0> == '1' then UNDEFINED;
case imm6 of
    when '001xxx'  esize = 8;  elements = 8;  shift_amount = UInt(imm6) - 8;
    when '01xxxx'  esize = 16;  elements = 4;  shift_amount = UInt(imm6) - 16;
    when '1xxxxx'  esize = 32;  elements = 2;  shift_amount = UInt(imm6) - 32;
if shift_amount == 0 then SEE "VMOVL";
unsigned = (U == '1');  d = UInt(D:Vd);  m = UInt(M:Vm);

A2

313029282726252423222120191817161514131211109876543210
111100111D11size10Vd001100M0Vm

A2

VSHLL{<c>}{<q>}.<type><size> <Qd>, <Dm>, #<imm>

if size == '11' || Vd<0> == '1' then UNDEFINED;
esize = 8 << UInt(size);  elements = 64 DIV esize;  shift_amount = esize;
unsigned = FALSE;  // Or TRUE without change of functionality
d = UInt(D:Vd);  m = UInt(M:Vm);

T1

15141312111098765432101514131211109876543210
111U11111Dimm6Vd101000M1Vm

T1 (imm6 != 000xxx)

VSHLL{<c>}{<q>}.<type><size> <Qd>, <Dm>, #<imm>

if imm6 == '000xxx' then SEE "Related encodings";
if Vd<0> == '1' then UNDEFINED;
case imm6 of
    when '001xxx'  esize = 8;  elements = 8;  shift_amount = UInt(imm6) - 8;
    when '01xxxx'  esize = 16;  elements = 4;  shift_amount = UInt(imm6) - 16;
    when '1xxxxx'  esize = 32;  elements = 2;  shift_amount = UInt(imm6) - 32;
if shift_amount == 0 then SEE "VMOVL";
unsigned = (U == '1');  d = UInt(D:Vd);  m = UInt(M:Vm);

T2

15141312111098765432101514131211109876543210
111111111D11size10Vd001100M0Vm

T2

VSHLL{<c>}{<q>}.<type><size> <Qd>, <Dm>, #<imm>

if size == '11' || Vd<0> == '1' then UNDEFINED;
esize = 8 << UInt(size);  elements = 64 DIV esize;  shift_amount = esize;
unsigned = FALSE;  // Or TRUE without change of functionality
d = UInt(D:Vd);  m = UInt(M:Vm);

Related encodings: See Advanced SIMD one register and modified immediate for the T32 instruction set, or Advanced SIMD one register and modified immediate for the A32 instruction set.

Assembler Symbols

<c>

For encoding A1 and A2: see Standard assembler syntax fields. This encoding must be unconditional.

For encoding T1 and T2: see Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<type>

The data type for the elements of the operand. It must be one of:

S
Signed. In encoding T1/A1, encoded as U = 0.
U
Unsigned. In encoding T1/A1, encoded as U = 1.
I
Untyped integer, Available only in encoding T2/A2.
<size>

The data size for the elements of the operand. The following table shows the permitted values and their encodings:

<size> Encoding T1/A1 Encoding T2/A2
8 Encoded as imm6<5:3> = 0b001 Encoded as size = 0b00
16 Encoded as imm6<5:4> = 0b01 Encoded as size = 0b01
32 Encoded as imm6<5> = 1 Encoded as size = 0b10
<Qd>

Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Dm>

Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

<imm>

The immediate value. <imm> must lie in the range 1 to <size>, and:

  • If <size> == <imm>, the encoding is T2/A2.
  • Otherwise, the encoding is T1/A1, and:
    • If <size> == 8, <imm> is encoded in imm6<2:0>.
    • If <size> == 16, <imm> is encoded in imm6<3:0>.
    • If <size> == 32, <imm> is encoded in imm6<4:0>.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for e = 0 to elements-1
        result = Int(Elem[Din[m],e,esize], unsigned) << shift_amount;
        Elem[Q[d>>1],e,2*esize] = result<2*esize-1:0>;

Operational information

If CPSR.DIT is 1 and this instruction passes its condition execution check:

  • The execution time of this instruction is independent of:
    • The values of the data supplied in any of its registers.
    • The values of the NZCV flags.
  • The response of this instruction to asynchronous exceptions does not vary based on:
    • The values of the data supplied in any of its registers.
    • The values of the NZCV flags.
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