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Top-level encodings for A32

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond op0 op1

Data-processing and miscellaneous instructions

These instructions are under the top-level.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 00 op0 op1 op2 op3 op4

Extra load/store

These instructions are under Data-processing and miscellaneous instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 000 op0 1 != 00 1

Load/Store Dual, Half, Signed Byte (register)

These instructions are under Extra load/store.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 P U 0 W o1 Rn Rt (0) (0) (0) (0) 1 != 00 1 Rm
cond op2

The following constraints also apply to this encoding: cond != 1111 && op2 != 00 && cond != 1111 && op2 != 00

Decode fields Instruction Details
P W o1 op2
0 0 0 01 STRH (register)post-indexed
0 0 0 10 LDRD (register)post-indexed
0 0 0 11 STRD (register)post-indexed
0 0 1 01 LDRH (register)post-indexed
0 0 1 10 LDRSB (register)post-indexed
0 0 1 11 LDRSH (register)post-indexed
0 1 0 01 STRHT
0 1 0 10 UNALLOCATED
0 1 0 11 UNALLOCATED
0 1 1 01 LDRHT
0 1 1 10 LDRSBT
0 1 1 11 LDRSHT
1 0 01 STRH (register)pre-indexed
1 0 10 LDRD (register)pre-indexed
1 0 11 STRD (register)pre-indexed
1 1 01 LDRH (register)pre-indexed
1 1 10 LDRSB (register)pre-indexed
1 1 11 LDRSH (register)pre-indexed

Load/Store Dual, Half, Signed Byte (immediate, literal)

These instructions are under Extra load/store.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 P U 1 W o1 Rn Rt imm4H 1 != 00 1 imm4L
cond op2

The following constraints also apply to this encoding: cond != 1111 && op2 != 00 && cond != 1111 && op2 != 00

Decode fields Instruction Details
P:W o1 Rn op2
0 1111 10 LDRD (literal)
!= 01 1 1111 01 LDRH (literal)
!= 01 1 1111 10 LDRSB (literal)
!= 01 1 1111 11 LDRSH (literal)
00 0 != 1111 10 LDRD (immediate)post-indexed
00 0 01 STRH (immediate)post-indexed
00 0 11 STRD (immediate)post-indexed
00 1 != 1111 01 LDRH (immediate)post-indexed
00 1 != 1111 10 LDRSB (immediate)post-indexed
00 1 != 1111 11 LDRSH (immediate)post-indexed
01 0 != 1111 10 UNALLOCATED
01 0 01 STRHT
01 0 11 UNALLOCATED
01 1 01 LDRHT
01 1 10 LDRSBT
01 1 11 LDRSHT
10 0 != 1111 10 LDRD (immediate)offset
10 0 01 STRH (immediate)offset
10 0 11 STRD (immediate)offset
10 1 != 1111 01 LDRH (immediate)offset
10 1 != 1111 10 LDRSB (immediate)offset
10 1 != 1111 11 LDRSH (immediate)offset
11 0 != 1111 10 LDRD (immediate)pre-indexed
11 0 01 STRH (immediate)pre-indexed
11 0 11 STRD (immediate)pre-indexed
11 1 != 1111 01 LDRH (immediate)pre-indexed
11 1 != 1111 10 LDRSB (immediate)pre-indexed
11 1 != 1111 11 LDRSH (immediate)pre-indexed

Multiply and Accumulate

These instructions are under Data-processing and miscellaneous instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 0 opc S RdHi RdLo Rm 1 0 0 1 Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc S
000 MUL, MULS
001 MLA, MLAS
010 0 UMAAL
010 1 UNALLOCATED
011 0 MLS
011 1 UNALLOCATED
100 UMULL, UMULLS
101 UMLAL, UMLALS
110 SMULL, SMULLS
111 SMLAL, SMLALS

Synchronization primitives and Load-Acquire/Store-Release

These instructions are under Data-processing and miscellaneous instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0001 op0 11 1001
Decode fields Instruction details
op0
0 UNALLOCATED
1 Load/Store Exclusive and Load-Acquire/Store-Release

Load/Store Exclusive and Load-Acquire/Store-Release

These instructions are under Synchronization primitives and Load-Acquire/Store-Release.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 1 1 size L Rn xRd (1) (1) ex ord 1 0 0 1 xRt
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
size L ex ord
00 0 0 0 STL
00 0 0 1 UNALLOCATED
00 0 1 0 STLEX
00 0 1 1 STREX
00 1 0 0 LDA
00 1 0 1 UNALLOCATED
00 1 1 0 LDAEX
00 1 1 1 LDREX
01 0 0 UNALLOCATED
01 0 1 0 STLEXD
01 0 1 1 STREXD
01 1 0 UNALLOCATED
01 1 1 0 LDAEXD
01 1 1 1 LDREXD
10 0 0 0 STLB
10 0 0 1 UNALLOCATED
10 0 1 0 STLEXB
10 0 1 1 STREXB
10 1 0 0 LDAB
10 1 0 1 UNALLOCATED
10 1 1 0 LDAEXB
10 1 1 1 LDREXB
11 0 0 0 STLH
11 0 0 1 UNALLOCATED
11 0 1 0 STLEXH
11 0 1 1 STREXH
11 1 0 0 LDAH
11 1 0 1 UNALLOCATED
11 1 1 0 LDAEXH
11 1 1 1 LDREXH

Miscellaneous

These instructions are under Data-processing and miscellaneous instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 00010 op0 0 0 op1
Decode fields Instruction details
op0 op1
00 001 UNALLOCATED
00 010 UNALLOCATED
00 011 UNALLOCATED
00 110 UNALLOCATED
01 001 BX
01 010 BXJ
01 011 BLX (register)
01 110 UNALLOCATED
10 001 UNALLOCATED
10 010 UNALLOCATED
10 011 UNALLOCATED
10 110 UNALLOCATED
11 001 CLZ
11 010 UNALLOCATED
11 011 UNALLOCATED
11 110 ERET
111 Exception Generation
000 Move special register (register)
100 Cyclic Redundancy Check
101 Integer Saturating Arithmetic

Exception Generation

These instructions are under Miscellaneous.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 1 0 opc 0 imm12 0 1 1 1 imm4
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
00 HLT
01 BKPT
10 HVC
11 SMC

Move special register (register)

These instructions are under Miscellaneous.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 1 0 opc 0 mask Rd (0) (0) B m 0 0 0 0 Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc B
x0 0 MRS
x0 1 MRS (Banked register)
x1 0 MSR (register)
x1 1 MSR (Banked register)

Cyclic Redundancy Check

These instructions are under Miscellaneous.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 1 0 sz 0 Rn Rd (0) (0) C (0) 0 1 0 0 Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
sz C
00 0 CRC32CRC32B
00 1 CRC32CCRC32CB
01 0 CRC32CRC32H
01 1 CRC32CCRC32CH
10 0 CRC32CRC32W
10 1 CRC32CCRC32CW
11 CONSTRAINED UNPREDICTABLE

The behavior of the CONSTRAINED UNPREDICTABLE encodings in this table is described in CONSTRAINED UNPREDICTABLE behavior for A32 and T32 instruction encodings


Integer Saturating Arithmetic

These instructions are under Miscellaneous.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 1 0 opc 0 Rn Rd (0) (0) (0) (0) 0 1 0 1 Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
00 QADD
01 QSUB
10 QDADD
11 QDSUB

Halfword Multiply and Accumulate

These instructions are under Data-processing and miscellaneous instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 1 0 opc 0 Rd Ra Rm 1 M N 0 Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111


Data-processing register (immediate shift)

These instructions are under Data-processing and miscellaneous instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 000 op0 op1 0

The following constraints also apply to this encoding: op0:op1 != 100


Integer Data Processing (three register, immediate shift)

These instructions are under Data-processing register (immediate shift).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 0 opc S Rn Rd imm5 stype 0 Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111


Integer Test and Compare (two register, immediate shift)

These instructions are under Data-processing register (immediate shift).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 1 0 opc 1 Rn (0) (0) (0) (0) imm5 stype 0 Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
00 TST (register)
01 TEQ (register)
10 CMP (register)
11 CMN (register)

Logical Arithmetic (three register, immediate shift)

These instructions are under Data-processing register (immediate shift).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 1 1 opc S Rn Rd imm5 stype 0 Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
00 ORR, ORRS (register)
01 MOV, MOVS (register)
10 BIC, BICS (register)
11 MVN, MVNS (register)

Data-processing register (register shift)

These instructions are under Data-processing and miscellaneous instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 000 op0 op1 0 1

The following constraints also apply to this encoding: op0:op1 != 100


Integer Data Processing (three register, register shift)

These instructions are under Data-processing register (register shift).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 0 opc S Rn Rd Rs 0 stype 1 Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111


Integer Test and Compare (two register, register shift)

These instructions are under Data-processing register (register shift).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 1 0 opc 1 Rn (0) (0) (0) (0) Rs 0 stype 1 Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111


Logical Arithmetic (three register, register shift)

These instructions are under Data-processing register (register shift).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 0 1 1 opc S Rn Rd Rs 0 stype 1 Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111


Data-processing immediate

These instructions are under Data-processing and miscellaneous instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 001 op0 op1

Integer Data Processing (two register and immediate)

These instructions are under Data-processing immediate.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 1 0 opc S Rn Rd imm12
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc S Rn
000 AND, ANDS (immediate)
001 EOR, EORS (immediate)
010 0 != 11x1 SUB, SUBS (immediate)SUB
010 0 1101 SUB, SUBS (SP minus immediate)SUB
010 0 1111 ADRA2
010 1 != 1101 SUB, SUBS (immediate)SUBS
010 1 1101 SUB, SUBS (SP minus immediate)SUBS
011 RSB, RSBS (immediate)
100 0 != 11x1 ADD, ADDS (immediate)ADD
100 0 1101 ADD, ADDS (SP plus immediate)ADD
100 0 1111 ADRA1
100 1 != 1101 ADD, ADDS (immediate)ADDS
100 1 1101 ADD, ADDS (SP plus immediate)ADDS
101 ADC, ADCS (immediate)
110 SBC, SBCS (immediate)
111 RSC, RSCS (immediate)

Move Halfword (immediate)

These instructions are under Data-processing immediate.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 1 1 0 H 0 0 imm4 Rd imm12
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
H
0 MOV, MOVS (immediate)
1 MOVT

Move Special Register and Hints (immediate)

These instructions are under Data-processing immediate.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 1 1 0 R 1 0 imm4 (1) (1) (1) (1) imm12
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details Architecture Version
R:imm4 imm12
!= 00000 MSR (immediate) -
00000 xxxx00000000 NOP -
00000 xxxx00000001 YIELD -
00000 xxxx00000010 WFE -
00000 xxxx00000011 WFI -
00000 xxxx00000100 SEV -
00000 xxxx00000101 SEVL -
00000 xxxx0000011x Reserved hint, behaves as NOP -
00000 xxxx00001xxx Reserved hint, behaves as NOP -
00000 xxxx00010000 ESB Armv8.2
00000 xxxx00010001 Reserved hint, behaves as NOP -
00000 xxxx00010010 TSB CSYNC Armv8.4
00000 xxxx00010011 Reserved hint, behaves as NOP -
00000 xxxx00010100 CSDB -
00000 xxxx00010101 Reserved hint, behaves as NOP -
00000 xxxx00011xxx Reserved hint, behaves as NOP -
00000 xxxx0001111x Reserved hint, behaves as NOP -
00000 xxxx001xxxxx Reserved hint, behaves as NOP -
00000 xxxx01xxxxxx Reserved hint, behaves as NOP -
00000 xxxx10xxxxxx Reserved hint, behaves as NOP -
00000 xxxx110xxxxx Reserved hint, behaves as NOP -
00000 xxxx1110xxxx Reserved hint, behaves as NOP -
00000 xxxx1111xxxx DBG -

Integer Test and Compare (one register and immediate)

These instructions are under Data-processing immediate.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 1 1 0 opc 1 Rn (0) (0) (0) (0) imm12
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
00 TST (immediate)
01 TEQ (immediate)
10 CMP (immediate)
11 CMN (immediate)

Logical Arithmetic (two register and immediate)

These instructions are under Data-processing immediate.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 0 1 1 1 opc S Rn Rd imm12
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Load/Store Word, Unsigned Byte (immediate, literal)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 1 0 P U o2 W o1 Rn Rt imm12
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
P:W o2 o1 Rn
!= 01 0 1 1111 LDR (literal)
!= 01 1 1 1111 LDRB (literal)
00 0 0 STR (immediate)post-indexed
00 0 1 != 1111 LDR (immediate)post-indexed
00 1 0 STRB (immediate)post-indexed
00 1 1 != 1111 LDRB (immediate)post-indexed
01 0 0 STRT
01 0 1 LDRT
01 1 0 STRBT
01 1 1 LDRBT
10 0 0 STR (immediate)offset
10 0 1 != 1111 LDR (immediate)offset
10 1 0 STRB (immediate)offset
10 1 1 != 1111 LDRB (immediate)offset
11 0 0 STR (immediate)pre-indexed
11 0 1 != 1111 LDR (immediate)pre-indexed
11 1 0 STRB (immediate)pre-indexed
11 1 1 != 1111 LDRB (immediate)pre-indexed

Load/Store Word, Unsigned Byte (register)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 1 1 P U o2 W o1 Rn Rt imm5 stype 0 Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
P o2 W o1
0 0 0 0 STR (register)post-indexed
0 0 0 1 LDR (register)post-indexed
0 0 1 0 STRT
0 0 1 1 LDRT
0 1 0 0 STRB (register)post-indexed
0 1 0 1 LDRB (register)post-indexed
0 1 1 0 STRBT
0 1 1 1 LDRBT
1 0 0 STR (register)pre-indexed
1 0 1 LDR (register)pre-indexed
1 1 0 STRB (register)pre-indexed
1 1 1 LDRB (register)pre-indexed

Media instructions

These instructions are under the top-level.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 011 op0 op1 1
Decode fields Instruction details
op0 op1
00xxx Parallel Arithmetic
01000 101 SEL
01000 001 UNALLOCATED
01000 xx0 PKHBT, PKHTB
01001 x01 UNALLOCATED
01001 xx0 UNALLOCATED
0110x x01 UNALLOCATED
0110x xx0 UNALLOCATED
01x10 001 Saturate 16-bit
01x10 101 UNALLOCATED
01x11 x01 Reverse Bit/Byte
01x1x xx0 Saturate 32-bit
01xxx 111 UNALLOCATED
01xxx 011 Extend and Add
10xxx Signed multiply, Divide
11000 000 Unsigned Sum of Absolute Differences
11000 100 UNALLOCATED
11001 x00 UNALLOCATED
1101x x00 UNALLOCATED
110xx 111 UNALLOCATED
1110x 111 UNALLOCATED
1110x x00 Bitfield Insert
11110 111 UNALLOCATED
11111 111 Permanently UNDEFINED
1111x x00 UNALLOCATED
11x0x x10 UNALLOCATED
11x1x x10 Bitfield Extract
11xxx 011 UNALLOCATED
11xxx x01 UNALLOCATED

Parallel Arithmetic

These instructions are under Media instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 1 1 0 0 op1 Rn Rd (1) (1) (1) (1) B op2 1 Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
op1 B op2
000 UNALLOCATED
001 0 00 SADD16
001 0 01 SASX
001 0 10 SSAX
001 0 11 SSUB16
001 1 00 SADD8
001 1 01 UNALLOCATED
001 1 10 UNALLOCATED
001 1 11 SSUB8
010 0 00 QADD16
010 0 01 QASX
010 0 10 QSAX
010 0 11 QSUB16
010 1 00 QADD8
010 1 01 UNALLOCATED
010 1 10 UNALLOCATED
010 1 11 QSUB8
011 0 00 SHADD16
011 0 01 SHASX
011 0 10 SHSAX
011 0 11 SHSUB16
011 1 00 SHADD8
011 1 01 UNALLOCATED
011 1 10 UNALLOCATED
011 1 11 SHSUB8
100 UNALLOCATED
101 0 00 UADD16
101 0 01 UASX
101 0 10 USAX
101 0 11 USUB16
101 1 00 UADD8
101 1 01 UNALLOCATED
101 1 10 UNALLOCATED
101 1 11 USUB8
110 0 00 UQADD16
110 0 01 UQASX
110 0 10 UQSAX
110 0 11 UQSUB16
110 1 00 UQADD8
110 1 01 UNALLOCATED
110 1 10 UNALLOCATED
110 1 11 UQSUB8
111 0 00 UHADD16
111 0 01 UHASX
111 0 10 UHSAX
111 0 11 UHSUB16
111 1 00 UHADD8
111 1 01 UNALLOCATED
111 1 10 UNALLOCATED
111 1 11 UHSUB8

Saturate 16-bit

These instructions are under Media instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 1 1 0 1 U 1 0 sat_imm Rd (1) (1) (1) (1) 0 0 1 1 Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
U
0 SSAT16
1 USAT16

Reverse Bit/Byte

These instructions are under Media instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 1 1 0 1 o1 1 1 (1) (1) (1) (1) Rd (1) (1) (1) (1) o2 0 1 1 Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
o1 o2
0 0 REV
0 1 REV16
1 0 RBIT
1 1 REVSH

Saturate 32-bit

These instructions are under Media instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 1 1 0 1 U 1 sat_imm Rd imm5 sh 0 1 Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
U
0 SSAT
1 USAT

Extend and Add

These instructions are under Media instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 1 1 0 1 U op Rn Rd rotate (0) (0) 0 1 1 1 Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
U op Rn
0 00 != 1111 SXTAB16
0 00 1111 SXTB16
0 10 != 1111 SXTAB
0 10 1111 SXTB
0 11 != 1111 SXTAH
0 11 1111 SXTH
1 00 != 1111 UXTAB16
1 00 1111 UXTB16
1 10 != 1111 UXTAB
1 10 1111 UXTB
1 11 != 1111 UXTAH
1 11 1111 UXTH

Signed multiply, Divide

These instructions are under Media instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 1 1 1 0 op1 Rd Ra Rm op2 1 Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
op1 Ra op2
000 != 1111 000 SMLAD, SMLADXSMLAD
000 != 1111 001 SMLAD, SMLADXSMLADX
000 != 1111 010 SMLSD, SMLSDXSMLSD
000 != 1111 011 SMLSD, SMLSDXSMLSDX
000 1xx UNALLOCATED
000 1111 000 SMUAD, SMUADXSMUAD
000 1111 001 SMUAD, SMUADXSMUADX
000 1111 010 SMUSD, SMUSDXSMUSD
000 1111 011 SMUSD, SMUSDXSMUSDX
001 000 SDIV
001 != 000 UNALLOCATED
010 UNALLOCATED
011 000 UDIV
011 != 000 UNALLOCATED
100 000 SMLALD, SMLALDXSMLALD
100 001 SMLALD, SMLALDXSMLALDX
100 010 SMLSLD, SMLSLDXSMLSLD
100 011 SMLSLD, SMLSLDXSMLSLDX
100 1xx UNALLOCATED
101 != 1111 000 SMMLA, SMMLARSMMLA
101 != 1111 001 SMMLA, SMMLARSMMLAR
101 01x UNALLOCATED
101 10x UNALLOCATED
101 110 SMMLS, SMMLSRSMMLS
101 111 SMMLS, SMMLSRSMMLSR
101 1111 000 SMMUL, SMMULRSMMUL
101 1111 001 SMMUL, SMMULRSMMULR
11x UNALLOCATED

Unsigned Sum of Absolute Differences

These instructions are under Media instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 1 1 1 1 0 0 0 Rd Ra Rm 0 0 0 1 Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
Ra
!= 1111 USADA8
1111 USAD8

Bitfield Insert

These instructions are under Media instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 1 1 1 1 1 0 msb Rd lsb 0 0 1 Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
Rn
!= 1111 BFI
1111 BFC

Permanently UNDEFINED

These instructions are under Media instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 1 1 1 1 1 1 1 imm12 1 1 1 1 imm4
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
cond
0xxx UNALLOCATED
10xx UNALLOCATED
110x UNALLOCATED
1110 UDF

Bitfield Extract

These instructions are under Media instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 0 1 1 1 1 U 1 widthm1 Rd lsb 1 0 1 Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
U
0 SBFX
1 UBFX

Branch, branch with link, and block data transfer

These instructions are under the top-level.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 10 op0
Decode fields Instruction details
cond op0
1111 0 Exception Save/Restore
!= 1111 0 Load/Store Multiple
1 Branch (immediate)

Exception Save/Restore

These instructions are under Branch, branch with link, and block data transfer.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 P U S W L Rn op mode

Load/Store Multiple

These instructions are under Branch, branch with link, and block data transfer.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 1 0 0 P U op W L Rn register_list
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
P U op L register_list
0 0 0 0 STMDA, STMED
0 0 0 1 LDMDA, LDMFA
0 1 0 0 STM, STMIA, STMEA
0 1 0 1 LDM, LDMIA, LDMFD
1 0 STM (User registers)
1 0 0 0 STMDB, STMFD
1 0 0 1 LDMDB, LDMEA
1 1 0xxxxxxxxxxxxxxx LDM (User registers)
1 1 0 0 STMIB, STMFA
1 1 0 1 LDMIB, LDMED
1 1 1xxxxxxxxxxxxxxx LDM (exception return)

Branch (immediate)

These instructions are under Branch, branch with link, and block data transfer.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 1 0 1 H imm24
Decode fields Instruction Details
cond H
!= 1111 0 B
!= 1111 1 BL, BLX (immediate)A1
1111 BL, BLX (immediate)A2

System register access, Advanced SIMD, floating-point, and Supervisor call

These instructions are under the top-level.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 11 op0 op1 op2
Decode fields Instruction details
cond op0 op1 op2
0x 0 UNALLOCATED
10 0 UNALLOCATED
11 Supervisor call
1111 != 11 1 Unconditional Advanced SIMD and floating-point instructions
!= 1111 0x 1 Advanced SIMD and System register load/store and 64-bit move
!= 1111 10 1 0 Floating-point data-processing
!= 1111 10 1 1 Advanced SIMD and System register 32-bit move

Supervisor call

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 1111
Decode fields Instruction details
cond
1111 UNALLOCATED
!= 1111 SVC

Unconditional Advanced SIMD and floating-point instructions

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
111111 op0 op1 1 op2 op3 op4 op5

The following constraints also apply to this encoding: op0<2:1> != 11


Advanced SIMD three registers of the same length extension

These instructions are under Unconditional Advanced SIMD and floating-point instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 0 op1 D op2 Vn Vd 1 op3 0 op4 N Q M U Vm
Decode fields Instruction Details Architecture Version
op1 op2 op3 op4 Q U
x1 0x 0 0 0 0 VCADD64-bit SIMD vector Armv8.3
x1 0x 0 0 0 1 UNALLOCATED -
x1 0x 0 0 1 0 VCADD128-bit SIMD vector Armv8.3
x1 0x 0 0 1 1 UNALLOCATED -
00 0x 0 0 UNALLOCATED -
00 0x 0 1 UNALLOCATED -
00 00 1 0 0 0 UNALLOCATED -
00 00 1 0 0 1 UNALLOCATED -
00 00 1 0 1 0 VMMLA Armv8.6
00 00 1 0 1 1 UNALLOCATED -
00 00 1 1 0 0 VDOT (vector)64-bit SIMD vector Armv8.6
00 00 1 1 0 1 UNALLOCATED -
00 00 1 1 1 0 VDOT (vector)128-bit SIMD vector Armv8.6
00 00 1 1 1 1 UNALLOCATED -
00 01 1 0 UNALLOCATED -
00 01 1 1 UNALLOCATED -
00 10 0 0 1 VFMAL (vector) Armv8.2
00 10 0 1 UNALLOCATED -
00 10 1 0 0 UNALLOCATED -
00 10 1 0 1 0 VSMMLA Armv8.6
00 10 1 0 1 1 VUMMLA Armv8.6
00 10 1 1 0 0 VSDOT (vector)64-bit SIMD vector Armv8.2
00 10 1 1 0 1 VUDOT (vector)64-bit SIMD vector Armv8.2
00 10 1 1 1 0 VSDOT (vector)128-bit SIMD vector Armv8.2
00 10 1 1 1 1 VUDOT (vector)128-bit SIMD vector Armv8.2
00 11 0 0 1 VFMAB, VFMAT (BFloat16, vector) Armv8.6
00 11 0 1 UNALLOCATED -
00 11 1 0 UNALLOCATED -
00 11 1 1 UNALLOCATED -
01 10 0 0 1 VFMSL (vector) Armv8.2
01 10 0 1 UNALLOCATED -
01 10 1 0 0 UNALLOCATED -
01 10 1 0 1 0 VUSMMLA Armv8.6
01 10 1 0 1 1 UNALLOCATED -
01 10 1 1 0 0 VUSDOT (vector)64-bit SIMD vector Armv8.6
01 10 1 1 1 UNALLOCATED -
01 10 1 1 1 0 VUSDOT (vector)128-bit SIMD vector Armv8.6
01 11 0 1 UNALLOCATED -
01 11 1 0 UNALLOCATED -
01 11 1 1 UNALLOCATED -
1x 0 0 0 VCMLA Armv8.3
10 11 0 1 UNALLOCATED -
10 11 1 0 UNALLOCATED -
10 11 1 1 UNALLOCATED -
11 11 0 1 UNALLOCATED -
11 11 1 0 UNALLOCATED -
11 11 1 1 UNALLOCATED -

Floating-point minNum/maxNum

These instructions are under Unconditional Advanced SIMD and floating-point instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 0 1 D 0 0 Vn Vd 1 0 != 00 N op M 0 Vm
size

The following constraints also apply to this encoding: size != 00 && size != 00

Decode fields Instruction Details
op
0 VMAXNM
1 VMINNM

Floating-point extraction and insertion

These instructions are under Unconditional Advanced SIMD and floating-point instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 0 1 D 1 1 0 0 0 0 Vd 1 0 != 00 op 1 M 0 Vm
size

The following constraints also apply to this encoding: size != 00 && size != 00

Decode fields Instruction Details Architecture Version
size op
01 UNALLOCATED -
10 0 VMOVX Armv8.2
10 1 VINS Armv8.2
11 UNALLOCATED -

Floating-point directed convert to integer

These instructions are under Unconditional Advanced SIMD and floating-point instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 0 1 D 1 1 1 o1 RM Vd 1 0 != 00 op 1 M 0 Vm
size

The following constraints also apply to this encoding: size != 00 && size != 00


Advanced SIMD and floating-point multiply with accumulate

These instructions are under Unconditional Advanced SIMD and floating-point instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 0 op1 D op2 Vn Vd 1 0 0 0 N Q M U Vm
Decode fields Instruction Details Architecture Version
op1 op2 Q U
0 0 VCMLA (by element)128-bit SIMD vector of half-precision floating-point Armv8.3
0 00 1 VFMAL (by scalar) Armv8.2
0 01 1 VFMSL (by scalar) Armv8.2
0 10 1 UNALLOCATED -
0 11 1 VFMAB, VFMAT (BFloat16, by scalar) Armv8.6
1 0 0 VCMLA (by element)64-bit SIMD vector of single-precision floating-point Armv8.3
1 1 UNALLOCATED -
1 1 0 VCMLA (by element)128-bit SIMD vector of single-precision floating-point Armv8.3

Advanced SIMD and floating-point dot product

These instructions are under Unconditional Advanced SIMD and floating-point instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 0 op1 D op2 Vn Vd 1 1 0 op4 N Q M U Vm
Decode fields Instruction Details Architecture Version
op1 op2 op4 Q U
0 00 0 UNALLOCATED -
0 00 1 0 0 VDOT (by element)64-bit SIMD vector Armv8.6
0 00 1 1 UNALLOCATED -
0 00 1 1 0 VDOT (by element)128-bit SIMD vector Armv8.6
0 01 0 UNALLOCATED -
0 10 0 UNALLOCATED -
0 10 1 0 0 VSDOT (by element)64-bit SIMD vector Armv8.2
0 10 1 0 1 VUDOT (by element)64-bit SIMD vector Armv8.2
0 10 1 1 0 VSDOT (by element)128-bit SIMD vector Armv8.2
0 10 1 1 1 VUDOT (by element)128-bit SIMD vector Armv8.2
0 11 UNALLOCATED -
1 0 UNALLOCATED -
1 00 1 0 0 VUSDOT (by element)64-bit SIMD vector Armv8.6
1 00 1 0 1 VSUDOT (by element)64-bit SIMD vector Armv8.6
1 00 1 1 0 VUSDOT (by element)128-bit SIMD vector Armv8.6
1 00 1 1 1 VSUDOT (by element)128-bit SIMD vector Armv8.6
1 01 1 UNALLOCATED -
1 1x 1 UNALLOCATED -

Advanced SIMD and System register load/store and 64-bit move

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 110 op0 1 op1
Decode fields Instruction details
op0 op1
00x0 0x Advanced SIMD and floating-point 64-bit move
00x0 11 System register 64-bit move
!= 00x0 0x Advanced SIMD and floating-point load/store
!= 00x0 11 System register load/store
10 UNALLOCATED

Advanced SIMD and floating-point 64-bit move

These instructions are under Advanced SIMD and System register load/store and 64-bit move.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 1 1 0 0 0 D 0 op Rt2 Rt 1 0 size opc2 M o3 Vm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111


System register 64-bit move

These instructions are under Advanced SIMD and System register load/store and 64-bit move.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 1 1 0 0 0 D 0 L Rt2 Rt 1 1 1 cp15 opc1 CRm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
D L
0 UNALLOCATED
1 0 MCRR
1 1 MRRC

Advanced SIMD and floating-point load/store

These instructions are under Advanced SIMD and System register load/store and 64-bit move.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 1 1 0 P U D W L Rn Vd 1 0 size imm8
cond

The following constraints also apply to this encoding: cond != 1111 && P:U:D:W != 00x0 && cond != 1111

Decode fields Instruction Details
P U W L Rn size imm8
0 0 1 UNALLOCATED
0 1 0x UNALLOCATED
0 1 0 10 VSTM, VSTMDB, VSTMIA
0 1 0 11 xxxxxxx0 VSTM, VSTMDB, VSTMIA
0 1 0 11 xxxxxxx1 FSTMDBX, FSTMIAXIncrement After
0 1 1 10 VLDM, VLDMDB, VLDMIA
0 1 1 11 xxxxxxx0 VLDM, VLDMDB, VLDMIA
0 1 1 11 xxxxxxx1 FLDM*X (FLDMDBX, FLDMIAX)Increment After
1 0 0 VSTR
1 0 1 != 1111 VLDR (immediate)
1 0 1 0x UNALLOCATED
1 0 1 0 10 VSTM, VSTMDB, VSTMIA
1 0 1 0 11 xxxxxxx0 VSTM, VSTMDB, VSTMIA
1 0 1 0 11 xxxxxxx1 FSTMDBX, FSTMIAXDecrement Before
1 0 1 1 10 VLDM, VLDMDB, VLDMIA
1 0 1 1 11 xxxxxxx0 VLDM, VLDMDB, VLDMIA
1 0 1 1 11 xxxxxxx1 FLDM*X (FLDMDBX, FLDMIAX)Decrement Before
1 0 1 1111 VLDR (literal)
1 1 1 UNALLOCATED

System register load/store

These instructions are under Advanced SIMD and System register load/store and 64-bit move.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 1 1 0 P U D W L Rn CRd 1 1 1 cp15 imm8
cond

The following constraints also apply to this encoding: cond != 1111 && P:U:D:W != 00x0 && cond != 1111

Decode fields Instruction Details
P:U:W D L Rn CRd cp15
!= 000 0 != 0101 0 UNALLOCATED
!= 000 0 1 1111 0101 0 LDC (literal)
!= 000 1 UNALLOCATED
!= 000 1 0101 0 UNALLOCATED
0x1 0 0 0101 0 STCpost-indexed
0x1 0 1 != 1111 0101 0 LDC (immediate)post-indexed
010 0 0 0101 0 STCunindexed
010 0 1 != 1111 0101 0 LDC (immediate)unindexed
1x0 0 0 0101 0 STCoffset
1x0 0 1 != 1111 0101 0 LDC (immediate)offset
1x1 0 0 0101 0 STCpre-indexed
1x1 0 1 != 1111 0101 0 LDC (immediate)pre-indexed

Floating-point data-processing

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 1110 op0 10 op1 0

Floating-point data-processing (two registers)

These instructions are under Floating-point data-processing.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 1 1 1 0 1 D 1 1 o1 opc2 Vd 1 0 size o3 1 M 0 Vm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details Architecture Version
o1 opc2 size o3
00 UNALLOCATED -
0 000 01 0 UNALLOCATED -
0 000 1 VABS -
0 000 10 0 VMOV (register)single-precision scalar -
0 000 11 0 VMOV (register)double-precision scalar -
0 001 0 VNEG -
0 001 1 VSQRT -
0 010 0 VCVTBhalf-precision to double-precision -
0 010 01 UNALLOCATED -
0 010 1 VCVTThalf-precision to double-precision -
0 011 01 0 VCVTB (BFloat16) Armv8.6
0 011 01 1 VCVTT (BFloat16) Armv8.6
0 011 10 0 VCVTBsingle-precision to half-precision -
0 011 10 1 VCVTTsingle-precision to half-precision -
0 011 11 0 VCVTBdouble-precision to half-precision -
0 011 11 1 VCVTTdouble-precision to half-precision -
0 100 0 VCMPA1 -
0 100 1 VCMPEA1 -
0 101 0 VCMPA2 -
0 101 1 VCMPEA2 -
0 110 0 VRINTR -
0 110 1 VRINTZ (floating-point) -
0 111 0 VRINTX (floating-point) -
0 111 01 1 UNALLOCATED -
0 111 10 1 VCVT (between double-precision and single-precision)single-precision to double-precision -
0 111 11 1 VCVT (between double-precision and single-precision)double-precision to single-precision -
1 000 VCVT (integer to floating-point, floating-point) -
1 001 01 UNALLOCATED -
1 001 10 UNALLOCATED -
1 001 11 0 UNALLOCATED -
1 001 11 1 VJCVT Armv8.3
1 01x VCVT (between floating-point and fixed-point, floating-point) -
1 100 0 VCVTR -
1 100 1 VCVT (floating-point to integer, floating-point) -
1 101 0 VCVTR -
1 101 1 VCVT (floating-point to integer, floating-point) -
1 11x VCVT (between floating-point and fixed-point, floating-point) -

Floating-point move immediate

These instructions are under Floating-point data-processing.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 1 1 1 0 1 D 1 1 imm4H Vd 1 0 size (0) 0 (0) 0 imm4L
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details Architecture Version
size
00 UNALLOCATED -
01 VMOV (immediate)half-precision scalar Armv8.2
10 VMOV (immediate)single-precision scalar -
11 VMOV (immediate)double-precision scalar -

Floating-point data-processing (three registers)

These instructions are under Floating-point data-processing.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 1 1 1 0 o0 D o1 Vn Vd 1 0 size N o2 M 0 Vm
cond

The following constraints also apply to this encoding: cond != 1111 && o0:D:o1 != 1x11 && cond != 1111

Decode fields Instruction Details
o0:o1 size o2
!= 111 00 UNALLOCATED
000 0 VMLA (floating-point)
000 1 VMLS (floating-point)
001 0 VNMLS
001 1 VNMLA
010 0 VMUL (floating-point)
010 1 VNMUL
011 0 VADD (floating-point)
011 1 VSUB (floating-point)
100 0 VDIV
101 0 VFNMS
101 1 VFNMA
110 0 VFMA
110 1 VFMS

Advanced SIMD and System register 32-bit move

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 1110 op0 1 op1 1
Decode fields Instruction details Architecture version
op0 op1
000 000 UNALLOCATED -
000 001 VMOV (between general-purpose register and half-precision) Armv8.2
000 010 VMOV (between general-purpose register and single-precision) -
001 010 UNALLOCATED -
01x 010 UNALLOCATED -
10x 010 UNALLOCATED -
110 010 UNALLOCATED -
111 010 Floating-point move special register -
011 Advanced SIMD 8/16/32-bit element move/duplicate -
10x UNALLOCATED -
11x System register 32-bit move -

Floating-point move special register

These instructions are under Advanced SIMD and System register 32-bit move.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 1 1 1 0 1 1 1 L reg Rt 1 0 1 0 (0) (0) (0) 1 (0) (0) (0) (0)
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
L
0 VMSR
1 VMRS

Advanced SIMD 8/16/32-bit element move/duplicate

These instructions are under Advanced SIMD and System register 32-bit move.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 1 1 1 0 opc1 L Vn Rt 1 0 1 1 N opc2 1 (0) (0) (0) (0)
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc1 L opc2
0xx 0 VMOV (general-purpose register to scalar)
1 VMOV (scalar to general-purpose register)
1xx 0 0x VDUP (general-purpose register)
1xx 0 1x UNALLOCATED

System register 32-bit move

These instructions are under Advanced SIMD and System register 32-bit move.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!= 1111 1 1 1 0 opc1 L CRn Rt 1 1 1 cp15 opc2 1 CRm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
L
0 MCR
1 MRC

Unconditional instructions

These instructions are under the top-level.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
11110 op0 op1
Decode fields Instruction details
op0 op1
00 Miscellaneous
01 Advanced SIMD data-processing
1x 1 Memory hints and barriers
10 0 Advanced SIMD element or structure load/store
11 0 UNALLOCATED

Miscellaneous

These instructions are under Unconditional instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1111000 op0 op1
Decode fields Instruction details Architecture version
op0 op1
0xxxx UNALLOCATED -
10000 xx0x Change Process State -
10001 1000 UNALLOCATED -
10001 x100 UNALLOCATED -
10001 xx01 UNALLOCATED -
10001 0000 SETPAN Armv8.1
1000x 0111 UNALLOCATED -
10010 0111 CONSTRAINED UNPREDICTABLE -
10011 0111 UNALLOCATED -
1001x xx0x UNALLOCATED -
100xx 0011 UNALLOCATED -
100xx 0x10 UNALLOCATED -
100xx 1x1x UNALLOCATED -
101xx UNALLOCATED -
11xxx UNALLOCATED -

The behavior of the CONSTRAINED UNPREDICTABLE encodings in this table is described in CONSTRAINED UNPREDICTABLE behavior for A32 and T32 instruction encodings


Change Process State

These instructions are under Miscellaneous.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 0 1 0 0 0 0 imod M op (0) (0) (0) (0) (0) (0) E A I F 0 mode
Decode fields Instruction Details
imod M op mode
1 0xxxx SETEND
0 CPS, CPSID, CPSIE
1 1xxxx UNALLOCATED

Advanced SIMD data-processing

These instructions are under Unconditional instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1111001 op0 op1

Advanced SIMD three registers of the same length

These instructions are under Advanced SIMD data-processing.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 U 0 D size Vn Vd opc N Q M o1 Vm
Decode fields Instruction Details Architecture Version
U size opc Q o1
0 0x 1100 1 VFMA -
0 0x 1101 0 VADD (floating-point) -
0 0x 1101 1 VMLA (floating-point) -
0 0x 1110 0 VCEQ (register)A2 -
0 0x 1111 0 VMAX (floating-point) -
0 0x 1111 1 VRECPS -
0000 0 VHADD -
0 00 0001 1 VAND (register) -
0000 1 VQADD -
0001 0 VRHADD -
0 00 1100 0 SHA1C -
0010 0 VHSUB -
0 01 0001 1 VBIC (register) -
0010 1 VQSUB -
0011 0 VCGT (register)A1 -
0011 1 VCGE (register)A1 -
0 01 1100 0 SHA1P -
0 1x 1100 1 VFMS -
0 1x 1101 0 VSUB (floating-point) -
0 1x 1101 1 VMLS (floating-point) -
0 1x 1110 0 UNALLOCATED -
0 1x 1111 0 VMIN (floating-point) -
0 1x 1111 1 VRSQRTS -
0100 0 VSHL (register) -
0 1000 0 VADD (integer) -
0 10 0001 1 VORR (register) -
0 1000 1 VTST -
0100 1 VQSHL (register) -
0 1001 0 VMLA (integer) -
0101 0 VRSHL -
0101 1 VQRSHL -
0 1011 0 VQDMULH -
0 10 1100 0 SHA1M -
0 1011 1 VPADD (integer) -
0110 0 VMAX (integer) -
0 11 0001 1 VORN (register) -
0110 1 VMIN (integer) -
0111 0 VABD (integer) -
0111 1 VABA -
0 11 1100 0 SHA1SU0 -
1 0x 1101 0 VPADD (floating-point) -
1 0x 1101 1 VMUL (floating-point) -
1 0x 1110 0 VCGE (register)A2 -
1 0x 1110 1 VACGE -
1 0x 1111 0 0 VPMAX (floating-point) -
1 0x 1111 1 VMAXNM -
1 00 0001 1 VEOR -
1001 1 VMUL (integer and polynomial) -
1 00 1100 0 SHA256H -
1010 0 0 VPMAX (integer) -
1 01 0001 1 VBSL -
1010 0 1 VPMIN (integer) -
1010 1 UNALLOCATED -
1 01 1100 0 SHA256H2 -
1 1x 1101 0 VABD (floating-point) -
1 1x 1110 0 VCGT (register)A2 -
1 1x 1110 1 VACGT -
1 1x 1111 0 0 VPMIN (floating-point) -
1 1x 1111 1 VMINNM -
1 1000 0 VSUB (integer) -
1 10 0001 1 VBIT -
1 1000 1 VCEQ (register)A1 -
1 1001 0 VMLS (integer) -
1 1011 0 VQRDMULH -
1 10 1100 0 SHA256SU1 -
1 1011 1 VQRDMLAH Armv8.1
1 11 0001 1 VBIF -
1 1100 1 VQRDMLSH Armv8.1
1 1111 1 0 UNALLOCATED -

Advanced SIMD two registers, or three registers of different lengths

These instructions are under Advanced SIMD data-processing.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1111001 op0 1 op1 op2 op3 0

Advanced SIMD two registers misc

These instructions are under Advanced SIMD two registers, or three registers of different lengths.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1 1 D 1 1 size opc1 Vd 0 opc2 Q M 0 Vm
Decode fields Instruction Details Architecture Version
size opc1 opc2 Q
00 0000 VREV64 -
00 0001 VREV32 -
00 0010 VREV16 -
00 0011 UNALLOCATED -
00 010x VPADDL -
00 0110 0 AESE -
00 0110 1 AESD -
00 0111 0 AESMC -
00 0111 1 AESIMC -
00 1000 VCLS -
00 10 0000 VSWP -
00 1001 VCLZ -
00 1010 VCNT -
00 1011 VMVN (register) -
00 10 1100 1 UNALLOCATED -
00 110x VPADAL -
00 1110 VQABS -
00 1111 VQNEG -
01 x000 VCGT (immediate #0) -
01 x001 VCGE (immediate #0) -
01 x010 VCEQ (immediate #0) -
01 x011 VCLE (immediate #0) -
01 x100 VCLT (immediate #0) -
01 x110 VABS -
01 x111 VNEG -
01 0101 1 SHA1H -
01 10 1100 1 VCVT (from single-precision to BFloat16, Advanced SIMD) Armv8.6
10 0001 VTRN -
10 0010 VUZP -
10 0011 VZIP -
10 0100 0 VMOVN -
10 0100 1 VQMOVN, VQMOVUNVQMOVUN -
10 0101 VQMOVN, VQMOVUNVQMOVN -
10 0110 0 VSHLL -
10 0111 0 SHA1SU1 -
10 0111 1 SHA256SU0 -
10 1000 VRINTN (Advanced SIMD) -
10 1001 VRINTX (Advanced SIMD) -
10 1010 VRINTA (Advanced SIMD) -
10 1011 VRINTZ (Advanced SIMD) -
10 10 1100 1 UNALLOCATED -
10 1100 0 VCVT (between half-precision and single-precision, Advanced SIMD)single-precision to half-precision -
10 1101 VRINTM (Advanced SIMD) -
10 1110 0 VCVT (between half-precision and single-precision, Advanced SIMD)half-precision to single-precision -
10 1110 1 UNALLOCATED -
10 1111 VRINTP (Advanced SIMD) -
11 000x VCVTA (Advanced SIMD) -
11 001x VCVTN (Advanced SIMD) -
11 010x VCVTP (Advanced SIMD) -
11 011x VCVTM (Advanced SIMD) -
11 10x0 VRECPE -
11 10x1 VRSQRTE -
11 10 1100 1 UNALLOCATED -
11 11xx VCVT (between floating-point and integer, Advanced SIMD) -

Advanced SIMD duplicate (scalar)

These instructions are under Advanced SIMD two registers, or three registers of different lengths.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1 1 D 1 1 imm4 Vd 1 1 opc Q M 0 Vm
Decode fields Instruction Details
opc
000 VDUP (scalar)
001 UNALLOCATED
01x UNALLOCATED
1xx UNALLOCATED

Advanced SIMD three registers of different lengths

These instructions are under Advanced SIMD two registers, or three registers of different lengths.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 U 1 D != 11 Vn Vd opc N 0 M 0 Vm
size

The following constraints also apply to this encoding: size != 11 && size != 11

Decode fields Instruction Details
U opc
0000 VADDL
0001 VADDW
0010 VSUBL
0 0100 VADDHN
0011 VSUBW
0 0110 VSUBHN
0 1001 VQDMLAL
0101 VABAL
0 1011 VQDMLSL
0 1101 VQDMULL
0111 VABDL (integer)
1000 VMLAL (integer)
1010 VMLSL (integer)
1 0100 VRADDHN
1 0110 VRSUBHN
11x0 VMULL (integer and polynomial)
1 1001 UNALLOCATED
1 1011 UNALLOCATED
1 1101 UNALLOCATED
1111 UNALLOCATED

Advanced SIMD two registers and a scalar

These instructions are under Advanced SIMD two registers, or three registers of different lengths.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 Q 1 D != 11 Vn Vd opc N 1 M 0 Vm
size

The following constraints also apply to this encoding: size != 11 && size != 11

Decode fields Instruction Details Architecture Version
Q opc
000x VMLA (by scalar) -
0 0011 VQDMLAL -
0010 VMLAL (by scalar) -
0 0111 VQDMLSL -
010x VMLS (by scalar) -
0 1011 VQDMULL -
0110 VMLSL (by scalar) -
100x VMUL (by scalar) -
1 0011 UNALLOCATED -
1010 VMULL (by scalar) -
1 0111 UNALLOCATED -
1100 VQDMULH -
1101 VQRDMULH -
1 1011 UNALLOCATED -
1110 VQRDMLAH Armv8.1
1111 VQRDMLSH Armv8.1

Advanced SIMD shifts and immediate generation

These instructions are under Advanced SIMD data-processing.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1111001 1 op0 1
Decode fields Instruction details
op0
000xxxxxxxxxxx0 Advanced SIMD one register and modified immediate
!= 000xxxxxxxxxxx0 Advanced SIMD two registers and shift amount

Advanced SIMD one register and modified immediate

These instructions are under Advanced SIMD shifts and immediate generation.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode 0 Q op 1 imm4
Decode fields Instruction Details
cmode op
0xx0 0 VMOV (immediate)A1
0xx0 1 VMVN (immediate)A1
0xx1 0 VORR (immediate)A1
0xx1 1 VBIC (immediate)A1
10x0 0 VMOV (immediate)A3
10x0 1 VMVN (immediate)A2
10x1 0 VORR (immediate)A2
10x1 1 VBIC (immediate)A2
11xx 0 VMOV (immediate)A4
110x 1 VMVN (immediate)A3
1110 1 VMOV (immediate)A5
1111 1 UNALLOCATED

Advanced SIMD two registers and shift amount

These instructions are under Advanced SIMD shifts and immediate generation.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 U 1 D imm3H imm3L Vd opc L Q M 1 Vm

The following constraints also apply to this encoding: imm3H:imm3L:Vd:opc:L != 000xxxxxxxxxxx0

Decode fields Instruction Details
U imm3H:L imm3L opc Q
!= 0000 0000 VSHR
!= 0000 0001 VSRA
!= 0000 000 1010 0 VMOVL
!= 0000 0010 VRSHR
!= 0000 0011 VRSRA
!= 0000 0111 VQSHL, VQSHLU (immediate)VQSHL
!= 0000 1001 0 VQSHRN, VQSHRUNVQSHRN
!= 0000 1001 1 VQRSHRN, VQRSHRUNVQRSHRN
!= 0000 1010 0 VSHLL
!= 0000 11xx VCVT (between floating-point and fixed-point, Advanced SIMD)
0 != 0000 0101 VSHL (immediate)
0 != 0000 1000 0 VSHRN
0 != 0000 1000 1 VRSHRN
1 != 0000 0100 VSRI
1 != 0000 0101 VSLI
1 != 0000 0110 VQSHL, VQSHLU (immediate)VQSHLU
1 != 0000 1000 0 VQSHRN, VQSHRUNVQSHRUN
1 != 0000 1000 1 VQRSHRN, VQRSHRUNVQRSHRUN

Memory hints and barriers

These instructions are under Unconditional instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
111101 op0 1 op1
Decode fields Instruction details
op0 op1
00xx1 CONSTRAINED UNPREDICTABLE
01001 CONSTRAINED UNPREDICTABLE
01011 Barriers
011x1 CONSTRAINED UNPREDICTABLE
0xxx0 Preload (immediate)
1xxx0 0 Preload (register)
1xxx1 0 CONSTRAINED UNPREDICTABLE
1xxxx 1 UNALLOCATED

The behavior of the CONSTRAINED UNPREDICTABLE encodings in this table is described in CONSTRAINED UNPREDICTABLE behavior for A32 and T32 instruction encodings


Barriers

These instructions are under Memory hints and barriers.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 0 1 0 1 1 1 (1) (1) (1) (1) (1) (1) (1) (1) (0) (0) (0) (0) opcode option
Decode fields Instruction Details
opcode option
0000 CONSTRAINED UNPREDICTABLE
0001 CLREX
001x CONSTRAINED UNPREDICTABLE
0100 != 0x00 DSB
0100 0000 SSBB
0100 0100 PSSBB
0101 DMB
0110 ISB
0111 SB
1xxx CONSTRAINED UNPREDICTABLE

The behavior of the CONSTRAINED UNPREDICTABLE encodings in this table is described in CONSTRAINED UNPREDICTABLE behavior for A32 and T32 instruction encodings


Preload (immediate)

These instructions are under Memory hints and barriers.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 0 D U R 0 1 Rn (1) (1) (1) (1) imm12
Decode fields Instruction Details
D R Rn
0 0 Reserved hint, behaves as NOP
0 1 PLI (immediate, literal)
1 1111 PLD (literal)
1 0 != 1111 PLD, PLDW (immediate)preload write
1 1 != 1111 PLD, PLDW (immediate)preload read

Preload (register)

These instructions are under Memory hints and barriers.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 1 D U o2 0 1 Rn (1) (1) (1) (1) imm5 stype 0 Rm
Decode fields Instruction Details
D o2
0 0 Reserved hint, behaves as NOP
0 1 PLI (register)
1 0 PLD, PLDW (register)preload write
1 1 PLD, PLDW (register)preload read

Advanced SIMD element or structure load/store

These instructions are under Unconditional instructions.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
11110100 op0 0 op1

Advanced SIMD load/store multiple structures

These instructions are under Advanced SIMD element or structure load/store.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 0 0 0 D L 0 Rn Vd itype size align Rm

Advanced SIMD load single structure to all lanes

These instructions are under Advanced SIMD element or structure load/store.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 0 0 1 D L 0 Rn Vd 1 1 N size T a Rm

Advanced SIMD load/store single structure to one lane

These instructions are under Advanced SIMD element or structure load/store.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 0 0 1 D L 0 Rn Vd != 11 N index_align Rm
size

The following constraints also apply to this encoding: size != 11 && size != 11