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Top-level encodings for T32

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
op0 op1
Decode fields Instruction details
op0 op1
!= 111 16-bit
111 00 BT2
111 != 00 32-bit

16-bit

These instructions are under the top-level.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
op0

The following constraints also apply to this encoding: op0<5:3> != 111

Shift (immediate), add, subtract, move, and compare

These instructions are under 16-bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00 op0 op1 op2

Add, subtract (three low registers)

These instructions are under Shift (immediate), add, subtract, move, and compare.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 1 1 0 S Rm Rn Rd
Decode fields Instruction Details
S
0 ADD, ADDS (register)
1 SUB, SUBS (register)

Add, subtract (two low registers and immediate)

These instructions are under Shift (immediate), add, subtract, move, and compare.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 1 1 1 S imm3 Rn Rd
Decode fields Instruction Details
S
0 ADD, ADDS (immediate)
1 SUB, SUBS (immediate)

Add, subtract, compare, move (one low register and immediate)

These instructions are under Shift (immediate), add, subtract, move, and compare.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 op Rd imm8
Decode fields Instruction Details
op
00 MOV, MOVS (immediate)
01 CMP (immediate)
10 ADD, ADDS (immediate)
11 SUB, SUBS (immediate)


Special data instructions and branch and exchange

These instructions are under 16-bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
010001 op0
Decode fields Instruction details
op0
11 Branch and exchange
!= 11 Add, subtract, compare, move (two high registers)

Branch and exchange

These instructions are under Special data instructions and branch and exchange.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 1 1 1 L Rm (0) (0) (0)
Decode fields Instruction Details
L
0 BX
1 BLX (register)

Add, subtract, compare, move (two high registers)

These instructions are under Special data instructions and branch and exchange.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 1 != 11 D Rs Rd
op

The following constraints also apply to this encoding: op != 11 && op != 11

Decode fields Instruction Details
op D:Rd Rs
00 != 1101 != 1101 ADD, ADDS (register)
00 1101 ADD, ADDS (SP plus register)T1
00 1101 != 1101 ADD, ADDS (SP plus register)T2
01 CMP (register)
10 MOV, MOVS (register)

Load/store (register offset)

These instructions are under 16-bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 1 L B H Rm Rn Rt
Decode fields Instruction Details
L B H
0 0 0 STR (register)
0 0 1 STRH (register)
0 1 0 STRB (register)
0 1 1 LDRSB (register)
1 0 0 LDR (register)
1 0 1 LDRH (register)
1 1 0 LDRB (register)
1 1 1 LDRSH (register)

Load/store word/byte (immediate offset)

These instructions are under 16-bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 B L imm5 Rn Rt
Decode fields Instruction Details
B L
0 0 STR (immediate)
0 1 LDR (immediate)
1 0 STRB (immediate)
1 1 LDRB (immediate)

Load/store halfword (immediate offset)

These instructions are under 16-bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 0 L imm5 Rn Rt
Decode fields Instruction Details
L
0 STRH (immediate)
1 LDRH (immediate)

Load/store (SP-relative)

These instructions are under 16-bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 1 L Rt imm8
Decode fields Instruction Details
L
0 STR (immediate)
1 LDR (immediate)

Add PC/SP (immediate)

These instructions are under 16-bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 0 SP Rd imm8
Decode fields Instruction Details
SP
0 ADR
1 ADD, ADDS (SP plus immediate)

Miscellaneous 16-bit instructions

These instructions are under 16-bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1011 op0 op1 op2 op3
Decode fields Instruction details Architecture version
op0 op1 op2 op3
0000 Adjust SP (immediate) -
0010 Extend -
0110 00 0 SETPAN Armv8.1
0110 00 1 UNALLOCATED -
0110 01 Change Processor State -
0110 1x UNALLOCATED -
0111 UNALLOCATED -
1000 UNALLOCATED -
1010 10 HLT -
1010 != 10 Reverse bytes -
1110 BKPT -
1111 0000 Hints -
1111 != 0000 IT -
x0x1 CBNZ, CBZ -
x10x Push and Pop -

Adjust SP (immediate)

These instructions are under Miscellaneous 16-bit instructions.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 1 0 0 0 0 S imm7
Decode fields Instruction Details
S
0 ADD, ADDS (SP plus immediate)
1 SUB, SUBS (SP minus immediate)

Extend

These instructions are under Miscellaneous 16-bit instructions.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 1 0 0 1 0 U B Rm Rd
Decode fields Instruction Details
U B
0 0 SXTH
0 1 SXTB
1 0 UXTH
1 1 UXTB

Change Processor State

These instructions are under Miscellaneous 16-bit instructions.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 1 0 1 1 0 0 1 op flags
Decode fields Instruction Details
op flags
0 SETEND
1 CPS, CPSID, CPSIE

Reverse bytes

These instructions are under Miscellaneous 16-bit instructions.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 1 1 0 1 0 != 10 Rm Rd
op

The following constraints also apply to this encoding: op != 10 && op != 10

Decode fields Instruction Details
op
00 REV
01 REV16
11 REVSH

Hints

These instructions are under Miscellaneous 16-bit instructions.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 1 1 1 1 1 hint 0 0 0 0
Decode fields Instruction Details
hint
0000 NOP
0001 YIELD
0010 WFE
0011 WFI
0100 SEV
0101 SEVL
011x Reserved hint, behaves as NOP
1xxx Reserved hint, behaves as NOP

Push and Pop

These instructions are under Miscellaneous 16-bit instructions.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 1 L 1 0 P register_list
Decode fields Instruction Details
L
0 PUSH
1 POP

Load/store multiple

These instructions are under 16-bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 L Rn register_list
Decode fields Instruction Details
L
0 STM, STMIA, STMEA
1 LDM, LDMIA, LDMFD

Conditional branch, and Supervisor Call

These instructions are under 16-bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1101 op0
Decode fields Instruction details
op0
111x Exception generation
!= 111x BT1

Exception generation

These instructions are under Conditional branch, and Supervisor Call.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 1 1 1 1 S imm8
Decode fields Instruction Details
S
0 UDF
1 SVC

32-bit

These instructions are under the top-level.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
111 op0 op1 op3

The following constraints also apply to this encoding: op0<3:2> != 00

System register access, Advanced SIMD, and floating-point

These instructions are under 32-bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
111 op0 11 op1 op2 op3

Advanced SIMD data-processing

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
111 1111 op0 op1

Advanced SIMD three registers of the same length

These instructions are under Advanced SIMD data-processing.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 U 1 1 1 1 0 D size Vn Vd opc N Q M o1 Vm
Decode fields Instruction Details Architecture Version
U size opc Q o1
0 0x 1100 1 VFMA -
0 0x 1101 0 VADD (floating-point) -
0 0x 1101 1 VMLA (floating-point) -
0 0x 1110 0 VCEQ (register)T2 -
0 0x 1111 0 VMAX (floating-point) -
0 0x 1111 1 VRECPS -
0000 0 VHADD -
0 00 0001 1 VAND (register) -
0000 1 VQADD -
0001 0 VRHADD -
0 00 1100 0 SHA1C -
0010 0 VHSUB -
0 01 0001 1 VBIC (register) -
0010 1 VQSUB -
0011 0 VCGT (register)T1 -
0011 1 VCGE (register)T1 -
0 01 1100 0 SHA1P -
0 1x 1100 1 VFMS -
0 1x 1101 0 VSUB (floating-point) -
0 1x 1101 1 VMLS (floating-point) -
0 1x 1110 0 UNALLOCATED -
0 1x 1111 0 VMIN (floating-point) -
0 1x 1111 1 VRSQRTS -
0100 0 VSHL (register) -
0 1000 0 VADD (integer) -
0 10 0001 1 VORR (register) -
0 1000 1 VTST -
0100 1 VQSHL (register) -
0 1001 0 VMLA (integer) -
0101 0 VRSHL -
0101 1 VQRSHL -
0 1011 0 VQDMULH -
0 10 1100 0 SHA1M -
0 1011 1 VPADD (integer) -
0110 0 VMAX (integer) -
0 11 0001 1 VORN (register) -
0110 1 VMIN (integer) -
0111 0 VABD (integer) -
0111 1 VABA -
0 11 1100 0 SHA1SU0 -
1 0x 1101 0 VPADD (floating-point) -
1 0x 1101 1 VMUL (floating-point) -
1 0x 1110 0 VCGE (register)T2 -
1 0x 1110 1 VACGE -
1 0x 1111 0 0 VPMAX (floating-point) -
1 0x 1111 1 VMAXNM -
1 00 0001 1 VEOR -
1001 1 VMUL (integer and polynomial) -
1 00 1100 0 SHA256H -
1010 0 0 VPMAX (integer) -
1 01 0001 1 VBSL -
1010 0 1 VPMIN (integer) -
1010 1 UNALLOCATED -
1 01 1100 0 SHA256H2 -
1 1x 1101 0 VABD (floating-point) -
1 1x 1110 0 VCGT (register)T2 -
1 1x 1110 1 VACGT -
1 1x 1111 0 0 VPMIN (floating-point) -
1 1x 1111 1 VMINNM -
1 1000 0 VSUB (integer) -
1 10 0001 1 VBIT -
1 1000 1 VCEQ (register)T1 -
1 1001 0 VMLS (integer) -
1 1011 0 VQRDMULH -
1 10 1100 0 SHA256SU1 -
1 1011 1 VQRDMLAH Armv8.1
1 11 0001 1 VBIF -
1 1100 1 VQRDMLSH Armv8.1
1 1111 1 0 UNALLOCATED -

Advanced SIMD two registers, or three registers of different lengths

These instructions are under Advanced SIMD data-processing.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
111 op0 11111 op1 op2 op3 0

Advanced SIMD two registers misc

These instructions are under Advanced SIMD two registers, or three registers of different lengths.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1 1 D 1 1 size opc1 Vd 0 opc2 Q M 0 Vm
Decode fields Instruction Details Architecture Version
size opc1 opc2 Q
00 0000 VREV64 -
00 0001 VREV32 -
00 0010 VREV16 -
00 0011 UNALLOCATED -
00 010x VPADDL -
00 0110 0 AESE -
00 0110 1 AESD -
00 0111 0 AESMC -
00 0111 1 AESIMC -
00 1000 VCLS -
00 10 0000 VSWP -
00 1001 VCLZ -
00 1010 VCNT -
00 1011 VMVN (register) -
00 10 1100 1 UNALLOCATED -
00 110x VPADAL -
00 1110 VQABS -
00 1111 VQNEG -
01 x000 VCGT (immediate #0) -
01 x001 VCGE (immediate #0) -
01 x010 VCEQ (immediate #0) -
01 x011 VCLE (immediate #0) -
01 x100 VCLT (immediate #0) -
01 x110 VABS -
01 x111 VNEG -
01 0101 1 SHA1H -
01 10 1100 1 VCVT (from single-precision to BFloat16, Advanced SIMD) Armv8.6
10 0001 VTRN -
10 0010 VUZP -
10 0011 VZIP -
10 0100 0 VMOVN -
10 0100 1 VQMOVN, VQMOVUNVQMOVUN -
10 0101 VQMOVN, VQMOVUNVQMOVN -
10 0110 0 VSHLL -
10 0111 0 SHA1SU1 -
10 0111 1 SHA256SU0 -
10 1000 VRINTN (Advanced SIMD) -
10 1001 VRINTX (Advanced SIMD) -
10 1010 VRINTA (Advanced SIMD) -
10 1011 VRINTZ (Advanced SIMD) -
10 10 1100 1 UNALLOCATED -
10 1100 0 VCVT (between half-precision and single-precision, Advanced SIMD)single-precision to half-precision -
10 1101 VRINTM (Advanced SIMD) -
10 1110 0 VCVT (between half-precision and single-precision, Advanced SIMD)half-precision to single-precision -
10 1110 1 UNALLOCATED -
10 1111 VRINTP (Advanced SIMD) -
11 000x VCVTA (Advanced SIMD) -
11 001x VCVTN (Advanced SIMD) -
11 010x VCVTP (Advanced SIMD) -
11 011x VCVTM (Advanced SIMD) -
11 10x0 VRECPE -
11 10x1 VRSQRTE -
11 10 1100 1 UNALLOCATED -
11 11xx VCVT (between floating-point and integer, Advanced SIMD) -

Advanced SIMD duplicate (scalar)

These instructions are under Advanced SIMD two registers, or three registers of different lengths.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1 1 D 1 1 imm4 Vd 1 1 opc Q M 0 Vm
Decode fields Instruction Details
opc
000 VDUP (scalar)
001 UNALLOCATED
01x UNALLOCATED
1xx UNALLOCATED

Advanced SIMD three registers of different lengths

These instructions are under Advanced SIMD two registers, or three registers of different lengths.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 U 1 1 1 1 1 D != 11 Vn Vd opc N 0 M 0 Vm
size

The following constraints also apply to this encoding: size != 11 && size != 11

Decode fields Instruction Details
U opc
0000 VADDL
0001 VADDW
0010 VSUBL
0 0100 VADDHN
0011 VSUBW
0 0110 VSUBHN
0 1001 VQDMLAL
0101 VABAL
0 1011 VQDMLSL
0 1101 VQDMULL
0111 VABDL (integer)
1000 VMLAL (integer)
1010 VMLSL (integer)
1 0100 VRADDHN
1 0110 VRSUBHN
11x0 VMULL (integer and polynomial)
1 1001 UNALLOCATED
1 1011 UNALLOCATED
1 1101 UNALLOCATED
1111 UNALLOCATED

Advanced SIMD two registers and a scalar

These instructions are under Advanced SIMD two registers, or three registers of different lengths.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 Q 1 1 1 1 1 D != 11 Vn Vd opc N 1 M 0 Vm
size

The following constraints also apply to this encoding: size != 11 && size != 11

Decode fields Instruction Details Architecture Version
Q opc
000x VMLA (by scalar) -
0 0011 VQDMLAL -
0010 VMLAL (by scalar) -
0 0111 VQDMLSL -
010x VMLS (by scalar) -
0 1011 VQDMULL -
0110 VMLSL (by scalar) -
100x VMUL (by scalar) -
1 0011 UNALLOCATED -
1010 VMULL (by scalar) -
1 0111 UNALLOCATED -
1100 VQDMULH -
1101 VQRDMULH -
1 1011 UNALLOCATED -
1110 VQRDMLAH Armv8.1
1111 VQRDMLSH Armv8.1

Advanced SIMD shifts and immediate generation

These instructions are under Advanced SIMD data-processing.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
111 11111 op0 1
Decode fields Instruction details
op0
000xxxxxxxxxxx0 Advanced SIMD one register and modified immediate
!= 000xxxxxxxxxxx0 Advanced SIMD two registers and shift amount

Advanced SIMD one register and modified immediate

These instructions are under Advanced SIMD shifts and immediate generation.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 i 1 1 1 1 1 D 0 0 0 imm3 Vd cmode 0 Q op 1 imm4
Decode fields Instruction Details
cmode op
0xx0 0 VMOV (immediate)T1
0xx0 1 VMVN (immediate)T1
0xx1 0 VORR (immediate)T1
0xx1 1 VBIC (immediate)T1
10x0 0 VMOV (immediate)T3
10x0 1 VMVN (immediate)T2
10x1 0 VORR (immediate)T2
10x1 1 VBIC (immediate)T2
11xx 0 VMOV (immediate)T4
110x 1 VMVN (immediate)T3
1110 1 VMOV (immediate)T5
1111 1 UNALLOCATED

Advanced SIMD two registers and shift amount

These instructions are under Advanced SIMD shifts and immediate generation.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 U 1 1 1 1 1 D imm3H imm3L Vd opc L Q M 1 Vm

The following constraints also apply to this encoding: imm3H:imm3L:Vd:opc:L != 000xxxxxxxxxxx0

Decode fields Instruction Details
U imm3H:L imm3L opc Q
!= 0000 0000 VSHR
!= 0000 0001 VSRA
!= 0000 000 1010 0 VMOVL
!= 0000 0010 VRSHR
!= 0000 0011 VRSRA
!= 0000 0111 VQSHL, VQSHLU (immediate)VQSHL
!= 0000 1001 0 VQSHRN, VQSHRUNVQSHRN
!= 0000 1001 1 VQRSHRN, VQRSHRUNVQRSHRN
!= 0000 1010 0 VSHLL
!= 0000 11xx VCVT (between floating-point and fixed-point, Advanced SIMD)
0 != 0000 0101 VSHL (immediate)
0 != 0000 1000 0 VSHRN
0 != 0000 1000 1 VRSHRN
1 != 0000 0100 VSRI
1 != 0000 0101 VSLI
1 != 0000 0110 VQSHL, VQSHLU (immediate)VQSHLU
1 != 0000 1000 0 VQSHRN, VQSHRUNVQSHRUN
1 != 0000 1000 1 VQRSHRN, VQRSHRUNVQRSHRUN

Advanced SIMD and System register load/store and 64-bit move

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1110110 op0 1 op1
Decode fields Instruction details
op0 op1
00x0 0x Advanced SIMD and floating-point 64-bit move
00x0 11 System register 64-bit move
!= 00x0 0x Advanced SIMD and floating-point load/store
!= 00x0 11 System register Load/Store
10 UNALLOCATED

Advanced SIMD and floating-point 64-bit move

These instructions are under Advanced SIMD and System register load/store and 64-bit move.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 0 0 0 D 0 op Rt2 Rt 1 0 size opc2 M o3 Vm

System register 64-bit move

These instructions are under Advanced SIMD and System register load/store and 64-bit move.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 0 0 0 D 0 L Rt2 Rt 1 1 1 cp15 opc1 CRm
Decode fields Instruction Details
D L
0 UNALLOCATED
1 0 MCRR
1 1 MRRC

Advanced SIMD and floating-point load/store

These instructions are under Advanced SIMD and System register load/store and 64-bit move.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 0 P U D W L Rn Vd 1 0 size imm8

The following constraints also apply to this encoding: P:U:D:W != 00x0

Decode fields Instruction Details
P U W L Rn size imm8
0 0 1 UNALLOCATED
0 1 0x UNALLOCATED
0 1 0 10 VSTM, VSTMDB, VSTMIA
0 1 0 11 xxxxxxx0 VSTM, VSTMDB, VSTMIA
0 1 0 11 xxxxxxx1 FSTMDBX, FSTMIAXIncrement After
0 1 1 10 VLDM, VLDMDB, VLDMIA
0 1 1 11 xxxxxxx0 VLDM, VLDMDB, VLDMIA
0 1 1 11 xxxxxxx1 FLDM*X (FLDMDBX, FLDMIAX)Increment After
1 0 0 VSTR
1 0 1 != 1111 VLDR (immediate)
1 0 1 0x UNALLOCATED
1 0 1 0 10 VSTM, VSTMDB, VSTMIA
1 0 1 0 11 xxxxxxx0 VSTM, VSTMDB, VSTMIA
1 0 1 0 11 xxxxxxx1 FSTMDBX, FSTMIAXDecrement Before
1 0 1 1 10 VLDM, VLDMDB, VLDMIA
1 0 1 1 11 xxxxxxx0 VLDM, VLDMDB, VLDMIA
1 0 1 1 11 xxxxxxx1 FLDM*X (FLDMDBX, FLDMIAX)Decrement Before
1 0 1 1111 VLDR (literal)
1 1 1 UNALLOCATED

System register Load/Store

These instructions are under Advanced SIMD and System register load/store and 64-bit move.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 0 P U D W L Rn CRd 1 1 1 cp15 imm8

The following constraints also apply to this encoding: P:U:D:W != 00x0

Decode fields Instruction Details
P:U:W D L Rn CRd cp15
!= 000 != 0101 0 UNALLOCATED
!= 000 0 1 1111 0101 0 LDC (literal)
!= 000 1 UNALLOCATED
!= 000 1 0101 0 UNALLOCATED
0x1 0 0 0101 0 STCpost-indexed
0x1 0 1 != 1111 0101 0 LDC (immediate)post-indexed
010 0 0 0101 0 STCunindexed
010 0 1 != 1111 0101 0 LDC (immediate)unindexed
1x0 0 0 0101 0 STCoffset
1x0 0 1 != 1111 0101 0 LDC (immediate)offset
1x1 0 0 0101 0 STCpre-indexed
1x1 0 1 != 1111 0101 0 LDC (immediate)pre-indexed

Floating-point data-processing

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
11101110 op0 10 op1 0

Floating-point data-processing (two registers)

These instructions are under Floating-point data-processing.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 1 0 1 D 1 1 o1 opc2 Vd 1 0 size o3 1 M 0 Vm
Decode fields Instruction Details Architecture Version
o1 opc2 size o3
00 UNALLOCATED -
0 000 01 0 UNALLOCATED -
0 000 1 VABS -
0 000 10 0 VMOV (register)single-precision scalar -
0 000 11 0 VMOV (register)double-precision scalar -
0 001 0 VNEG -
0 001 1 VSQRT -
0 010 0 VCVTBhalf-precision to double-precision -
0 010 01 UNALLOCATED -
0 010 1 VCVTThalf-precision to double-precision -
0 011 01 0 VCVTB (BFloat16) Armv8.6
0 011 01 1 VCVTT (BFloat16) Armv8.6
0 011 10 0 VCVTBsingle-precision to half-precision -
0 011 10 1 VCVTTsingle-precision to half-precision -
0 011 11 0 VCVTBdouble-precision to half-precision -
0 011 11 1 VCVTTdouble-precision to half-precision -
0 100 0 VCMPT1 -
0 100 1 VCMPET1 -
0 101 0 VCMPT2 -
0 101 1 VCMPET2 -
0 110 0 VRINTR -
0 110 1 VRINTZ (floating-point) -
0 111 0 VRINTX (floating-point) -
0 111 01 1 UNALLOCATED -
0 111 10 1 VCVT (between double-precision and single-precision)single-precision to double-precision -
0 111 11 1 VCVT (between double-precision and single-precision)double-precision to single-precision -
1 000 VCVT (integer to floating-point, floating-point) -
1 001 01 UNALLOCATED -
1 001 10 UNALLOCATED -
1 001 11 0 UNALLOCATED -
1 001 11 1 VJCVT Armv8.3
1 01x VCVT (between floating-point and fixed-point, floating-point) -
1 100 0 VCVTR -
1 100 1 VCVT (floating-point to integer, floating-point) -
1 101 0 VCVTR -
1 101 1 VCVT (floating-point to integer, floating-point) -
1 11x VCVT (between floating-point and fixed-point, floating-point) -

Floating-point move immediate

These instructions are under Floating-point data-processing.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 1 0 1 D 1 1 imm4H Vd 1 0 size (0) 0 (0) 0 imm4L
Decode fields Instruction Details Architecture Version
size
00 UNALLOCATED -
01 VMOV (immediate)half-precision scalar Armv8.2
10 VMOV (immediate)single-precision scalar -
11 VMOV (immediate)double-precision scalar -

Floating-point data-processing (three registers)

These instructions are under Floating-point data-processing.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 1 0 o0 D o1 Vn Vd 1 0 size N o2 M 0 Vm

The following constraints also apply to this encoding: o0:D:o1 != 1x11

Decode fields Instruction Details
o0:o1 size o2
!= 111 00 UNALLOCATED
000 0 VMLA (floating-point)
000 1 VMLS (floating-point)
001 0 VNMLS
001 1 VNMLA
010 0 VMUL (floating-point)
010 1 VNMUL
011 0 VADD (floating-point)
011 1 VSUB (floating-point)
100 0 VDIV
101 0 VFNMS
101 1 VFNMA
110 0 VFMA
110 1 VFMS

Advanced SIMD and System register 32-bit move

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
11101110 op0 1 op1 1
Decode fields Instruction details Architecture version
op0 op1
000 000 UNALLOCATED -
000 001 VMOV (between general-purpose register and half-precision) Armv8.2
000 010 VMOV (between general-purpose register and single-precision) -
001 010 UNALLOCATED -
01x 010 UNALLOCATED -
10x 010 UNALLOCATED -
110 010 UNALLOCATED -
111 010 Floating-point move special register -
011 Advanced SIMD 8/16/32-bit element move/duplicate -
10x UNALLOCATED -
11x System register 32-bit move -

Floating-point move special register

These instructions are under Advanced SIMD and System register 32-bit move.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 1 0 1 1 1 L reg Rt 1 0 1 0 (0) (0) (0) 1 (0) (0) (0) (0)
Decode fields Instruction Details
L
0 VMSR
1 VMRS

Advanced SIMD 8/16/32-bit element move/duplicate

These instructions are under Advanced SIMD and System register 32-bit move.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 1 0 opc1 L Vn Rt 1 0 1 1 N opc2 1 (0) (0) (0) (0)
Decode fields Instruction Details
opc1 L opc2
0xx 0 VMOV (general-purpose register to scalar)
1 VMOV (scalar to general-purpose register)
1xx 0 0x VDUP (general-purpose register)
1xx 0 1x UNALLOCATED

System register 32-bit move

These instructions are under Advanced SIMD and System register 32-bit move.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 1 0 opc1 L CRn Rt 1 1 1 cp15 opc2 1 CRm
Decode fields Instruction Details
L
0 MCR
1 MRC

Additional Advanced SIMD and floating-point instructions

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
111111 op0 op1 1 op2 op3 op4 op5

The following constraints also apply to this encoding: op0<2:1> != 11


Advanced SIMD three registers of the same length extension

These instructions are under Additional Advanced SIMD and floating-point instructions.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 0 op1 D op2 Vn Vd 1 op3 0 op4 N Q M U Vm
Decode fields Instruction Details Architecture Version
op1 op2 op3 op4 Q U
x1 0x 0 0 0 0 VCADD64-bit SIMD vector Armv8.3
x1 0x 0 0 0 1 UNALLOCATED -
x1 0x 0 0 1 0 VCADD128-bit SIMD vector Armv8.3
x1 0x 0 0 1 1 UNALLOCATED -
00 0x 0 0 UNALLOCATED -
00 0x 0 1 UNALLOCATED -
00 00 1 0 0 0 UNALLOCATED -
00 00 1 0 0 1 UNALLOCATED -
00 00 1 0 1 0 VMMLA Armv8.6
00 00 1 0 1 1 UNALLOCATED -
00 00 1 1 0 0 VDOT (vector)64-bit SIMD vector Armv8.6
00 00 1 1 0 1 UNALLOCATED -
00 00 1 1 1 0 VDOT (vector)128-bit SIMD vector Armv8.6
00 00 1 1 1 1 UNALLOCATED -
00 01 1 0 UNALLOCATED -
00 01 1 1 UNALLOCATED -
00 10 0 0 1 VFMAL (vector) Armv8.2
00 10 0 1 UNALLOCATED -
00 10 1 0 0 UNALLOCATED -
00 10 1 0 1 0 VSMMLA Armv8.6
00 10 1 0 1 1 VUMMLA Armv8.6
00 10 1 1 0 0 VSDOT (vector)64-bit SIMD vector Armv8.2
00 10 1 1 0 1 VUDOT (vector)64-bit SIMD vector Armv8.2
00 10 1 1 1 0 VSDOT (vector)128-bit SIMD vector Armv8.2
00 10 1 1 1 1 VUDOT (vector)128-bit SIMD vector Armv8.2
00 11 0 0 1 VFMAB, VFMAT (BFloat16, vector) Armv8.6
00 11 0 1 UNALLOCATED -
00 11 1 0 UNALLOCATED -
00 11 1 1 UNALLOCATED -
01 10 0 0 1 VFMSL (vector) Armv8.2
01 10 0 1 UNALLOCATED -
01 10 1 0 0 UNALLOCATED -
01 10 1 0 1 0 VUSMMLA Armv8.6
01 10 1 0 1 1 UNALLOCATED -
01 10 1 1 0 0 VUSDOT (vector)64-bit SIMD vector Armv8.6
01 10 1 1 1 UNALLOCATED -
01 10 1 1 1 0 VUSDOT (vector)128-bit SIMD vector Armv8.6
01 11 0 1 UNALLOCATED -
01 11 1 0 UNALLOCATED -
01 11 1 1 UNALLOCATED -
1x 0 0 0 VCMLA Armv8.3
10 11 0 1 UNALLOCATED -
10 11 1 0 UNALLOCATED -
10 11 1 1 UNALLOCATED -
11 11 0 1 UNALLOCATED -
11 11 1 0 UNALLOCATED -
11 11 1 1 UNALLOCATED -

Floating-point minNum/maxNum

These instructions are under Additional Advanced SIMD and floating-point instructions.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 0 1 D 0 0 Vn Vd 1 0 != 00 N op M 0 Vm
size

The following constraints also apply to this encoding: size != 00 && size != 00

Decode fields Instruction Details
op
0 VMAXNM
1 VMINNM

Floating-point extraction and insertion

These instructions are under Additional Advanced SIMD and floating-point instructions.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 0 1 D 1 1 0 0 0 0 Vd 1 0 != 00 op 1 M 0 Vm
size

The following constraints also apply to this encoding: size != 00 && size != 00

Decode fields Instruction Details Architecture Version
size op
01 UNALLOCATED -
10 0 VMOVX Armv8.2
10 1 VINS Armv8.2
11 UNALLOCATED -

Floating-point directed convert to integer

These instructions are under Additional Advanced SIMD and floating-point instructions.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 0 1 D 1 1 1 o1 RM Vd 1 0 != 00 op 1 M 0 Vm
size

The following constraints also apply to this encoding: size != 00 && size != 00


Advanced SIMD and floating-point multiply with accumulate

These instructions are under Additional Advanced SIMD and floating-point instructions.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 0 op1 D op2 Vn Vd 1 0 0 0 N Q M U Vm
Decode fields Instruction Details Architecture Version
op1 op2 Q U
0 0 VCMLA (by element)128-bit SIMD vector of half-precision floating-point Armv8.3
0 00 1 VFMAL (by scalar) Armv8.2
0 01 1 VFMSL (by scalar) Armv8.2
0 10 1 UNALLOCATED -
0 11 1 VFMAB, VFMAT (BFloat16, by scalar) Armv8.6
1 0 0 VCMLA (by element)64-bit SIMD vector of single-precision floating-point Armv8.3
1 1 UNALLOCATED -
1 1 0 VCMLA (by element)128-bit SIMD vector of single-precision floating-point Armv8.3

Advanced SIMD and floating-point dot product

These instructions are under Additional Advanced SIMD and floating-point instructions.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 0 op1 D op2 Vn Vd 1 1 0 op4 N Q M U Vm
Decode fields Instruction Details Architecture Version
op1 op2 op4 Q U
0 00 0 UNALLOCATED -
0 00 1 0 0 VDOT (by element)64-bit SIMD vector Armv8.6
0 00 1 1 UNALLOCATED -
0 00 1 1 0 VDOT (by element)128-bit SIMD vector Armv8.6
0 01 0 UNALLOCATED -
0 10 0 UNALLOCATED -
0 10 1 0 0 VSDOT (by element)64-bit SIMD vector Armv8.2
0 10 1 0 1 VUDOT (by element)64-bit SIMD vector Armv8.2
0 10 1 1 0 VSDOT (by element)128-bit SIMD vector Armv8.2
0 10 1 1 1 VUDOT (by element)128-bit SIMD vector Armv8.2
0 11 UNALLOCATED -
1 0 UNALLOCATED -
1 00 1 0 0 VUSDOT (by element)64-bit SIMD vector Armv8.6
1 00 1 0 1 VSUDOT (by element)64-bit SIMD vector Armv8.6
1 00 1 1 0 VUSDOT (by element)128-bit SIMD vector Armv8.6
1 00 1 1 1 VSUDOT (by element)128-bit SIMD vector Armv8.6
1 01 1 UNALLOCATED -
1 1x 1 UNALLOCATED -

Load/store multiple

These instructions are under 32-bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 0 0 opc 0 W L Rn P M register_list

Load/store dual, load/store exclusive, load-acquire/store-release, and table branch

These instructions are under 32-bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1110100 op0 op1 op2 op3

The following constraints also apply to this encoding: op0<1> == 1

Decode fields Instruction details
op0 op1 op2 op3
0010 Load/store exclusive
0110 0 000 UNALLOCATED
0110 1 000 TBB, TBH
0110 01x Load/store exclusive byte/half/dual
0110 1xx Load-acquire / Store-release
0x11 != 1111 Load/store dual (immediate, post-indexed)
1x10 != 1111 Load/store dual (immediate)
1x11 != 1111 Load/store dual (immediate, pre-indexed)
!= 0xx0 1111 LDRD (literal)

Load/store exclusive

These instructions are under Load/store dual, load/store exclusive, load-acquire/store-release, and table branch.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 0 0 0 0 1 0 L Rn Rt Rd imm8
Decode fields Instruction Details
L
0 STREX
1 LDREX

Load/store exclusive byte/half/dual

These instructions are under Load/store dual, load/store exclusive, load-acquire/store-release, and table branch.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 0 0 0 1 1 0 L Rn Rt Rt2 0 1 sz Rd
Decode fields Instruction Details
L sz
0 00 STREXB
0 01 STREXH
0 10 UNALLOCATED
0 11 STREXD
1 00 LDREXB
1 01 LDREXH
1 10 UNALLOCATED
1 11 LDREXD

Load-acquire / Store-release

These instructions are under Load/store dual, load/store exclusive, load-acquire/store-release, and table branch.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 0 0 0 1 1 0 L Rn Rt Rt2 1 op sz Rd
Decode fields Instruction Details
L op sz
0 0 00 STLB
0 0 01 STLH
0 0 10 STL
0 0 11 UNALLOCATED
0 1 00 STLEXB
0 1 01 STLEXH
0 1 10 STLEX
0 1 11 STLEXD
1 0 00 LDAB
1 0 01 LDAH
1 0 10 LDA
1 0 11 UNALLOCATED
1 1 00 LDAEXB
1 1 01 LDAEXH
1 1 10 LDAEX
1 1 11 LDAEXD

Load/store dual (immediate, post-indexed)

These instructions are under Load/store dual, load/store exclusive, load-acquire/store-release, and table branch.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 0 0 0 U 1 1 L != 1111 Rt Rt2 imm8
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
L
0 STRD (immediate)
1 LDRD (immediate)

Load/store dual (immediate)

These instructions are under Load/store dual, load/store exclusive, load-acquire/store-release, and table branch.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 0 0 1 U 1 0 L != 1111 Rt Rt2 imm8
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
L
0 STRD (immediate)
1 LDRD (immediate)

Load/store dual (immediate, pre-indexed)

These instructions are under Load/store dual, load/store exclusive, load-acquire/store-release, and table branch.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 0 0 1 U 1 1 L != 1111 Rt Rt2 imm8
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
L
0 STRD (immediate)
1 LDRD (immediate)

Data-processing (shifted register)

These instructions are under 32-bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 0 1 op1 S Rn (0) imm3 Rd imm2 stype Rm
Decode fields Instruction Details
op1 S Rn imm3:imm2:stype Rd
0000 0 AND, ANDS (register)AND, rotate right with extend
0000 1 != 0000011 != 1111 AND, ANDS (register)ANDS, shift or rotate by value
0000 1 != 0000011 1111 TST (register)shift or rotate by value
0000 1 0000011 != 1111 AND, ANDS (register)ANDS, rotate right with extend
0000 1 0000011 1111 TST (register)rotate right with extend
0001 BIC, BICS (register)
0010 0 != 1111 ORR, ORRS (register)ORR
0010 0 1111 MOV, MOVS (register)MOV
0010 1 != 1111 ORR, ORRS (register)ORRS
0010 1 1111 MOV, MOVS (register)MOVS
0011 0 != 1111 ORN, ORNS (register)not flag setting
0011 0 1111 MVN, MVNS (register)MVN
0011 1 != 1111 ORN, ORNS (register)flag setting
0011 1 1111 MVN, MVNS (register)MVNS
0100 0 EOR, EORS (register)EOR, rotate right with extend
0100 1 != 0000011 != 1111 EOR, EORS (register)EORS, shift or rotate by value
0100 1 != 0000011 1111 TEQ (register)shift or rotate by value
0100 1 0000011 != 1111 EOR, EORS (register)EORS, rotate right with extend
0100 1 0000011 1111 TEQ (register)rotate right with extend
0101 UNALLOCATED
0110 0 xxxxx00 PKHBT, PKHTBPKHBT
0110 0 xxxxx01 UNALLOCATED
0110 0 xxxxx10 PKHBT, PKHTBPKHTB
0110 0 xxxxx11 UNALLOCATED
0111 UNALLOCATED
1000 0 != 1101 ADD, ADDS (register)ADD
1000 0 1101 ADD, ADDS (SP plus register)ADD
1000 1 != 1101 != 1111 ADD, ADDS (register)ADDS
1000 1 1101 != 1111 ADD, ADDS (SP plus register)ADDS
1000 1 1111 CMN (register)
1001 UNALLOCATED
1010 ADC, ADCS (register)
1011 SBC, SBCS (register)
1100 UNALLOCATED
1101 0 != 1101 SUB, SUBS (register)SUB
1101 0 1101 SUB, SUBS (SP minus register)SUB
1101 1 != 1101 != 1111 SUB, SUBS (register)SUBS
1101 1 1101 != 1111 SUB, SUBS (SP minus register)SUBS
1101 1 1111 CMP (register)
1110 RSB, RSBS (register)
1111 UNALLOCATED

Branches and miscellaneous control

These instructions are under 32-bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
11110 op0 op1 op2 1 op3 op4 op5
Decode fields Instruction details
op0 op1 op2 op3 op4 op5
0 1110 0x 0x0 0 MSR (register)
0 1110 0x 0x0 1 MSR (Banked register)
0 1110 10 0x0 000 Hints
0 1110 10 0x0 != 000 Change processor state
0 1110 11 0x0 Miscellaneous system
0 1111 00 0x0 BXJ
0 1111 01 0x0 Exception return
0 1111 1x 0x0 0 MRS
0 1111 1x 0x0 1 MRS (Banked register)
1 1110 00 000 DCPS
1 1110 00 010 UNALLOCATED
1 1110 01 0x0 UNALLOCATED
1 1110 1x 0x0 UNALLOCATED
1 1111 0x 0x0 UNALLOCATED
1 1111 1x 0x0 Exception generation
!= 111x 0x0 BT3
0x1 BT4
1x0 BL, BLX (immediate)T2
1x1 BL, BLX (immediate)T1

Hints

These instructions are under Branches and miscellaneous control.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1 1 0 1 0 (1) (1) (1) (1) 1 0 (0) 0 (0) 0 0 0 hint option
Decode fields Instruction Details Architecture Version
hint option
0000 0000 NOP -
0000 0001 YIELD -
0000 0010 WFE -
0000 0011 WFI -
0000 0100 SEV -
0000 0101 SEVL -
0000 011x Reserved hint, behaves as NOP -
0000 1xxx Reserved hint, behaves as NOP -
0001 0000 ESB Armv8.2
0001 0001 Reserved hint, behaves as NOP -
0001 0010 TSB CSYNC Armv8.4
0001 0011 Reserved hint, behaves as NOP -
0001 0100 CSDB -
0001 0101 Reserved hint, behaves as NOP -
0001 011x Reserved hint, behaves as NOP -
0001 1xxx Reserved hint, behaves as NOP -
001x Reserved hint, behaves as NOP -
01xx Reserved hint, behaves as NOP -
10xx Reserved hint, behaves as NOP -
110x Reserved hint, behaves as NOP -
1110 Reserved hint, behaves as NOP -
1111 DBG -

Change processor state

These instructions are under Branches and miscellaneous control.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1 1 0 1 0 (1) (1) (1) (1) 1 0 (0) 0 (0) imod M A I F mode

The following constraints also apply to this encoding: imod:M != 000

Decode fields Instruction Details
imod M
00 1 CPS, CPSID, CPSIECPS
01 UNALLOCATED
10 CPS, CPSID, CPSIECPSIE
11 CPS, CPSID, CPSIECPSID

Miscellaneous system

These instructions are under Branches and miscellaneous control.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1 1 0 1 1 (1) (1) (1) (1) 1 0 (0) 0 (1) (1) (1) (1) opc option
Decode fields Instruction Details
opc option
000x UNALLOCATED
0010 CLREX
0011 UNALLOCATED
0100 != 0x00 DSB
0100 0000 SSBB
0100 0100 PSSBB
0101 DMB
0110 ISB
0111 SB
1xxx UNALLOCATED

Exception return

These instructions are under Branches and miscellaneous control.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1 1 1 0 1 Rn 1 0 (0) 0 (1) (1) (1) (1) imm8
Decode fields Instruction Details
Rn imm8
!= 00000000 SUB, SUBS (immediate)
1110 00000000 ERET

DCPS

These instructions are under Branches and miscellaneous control.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 1 1 1 0 0 0 imm4 1 0 0 0 imm10 opt
Decode fields Instruction Details
imm4 imm10 opt
!= 1111 UNALLOCATED
1111 != 0000000000 UNALLOCATED
1111 0000000000 00 UNALLOCATED
1111 0000000000 01 DCPS1
1111 0000000000 10 DCPS2
1111 0000000000 11 DCPS3

Exception generation

These instructions are under Branches and miscellaneous control.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 1 1 1 1 1 o1 imm4 1 0 o2 0 imm12
Decode fields Instruction Details
o1 o2
0 0 HVC
0 1 UNALLOCATED
1 0 SMC
1 1 UDF

Data-processing (modified immediate)

These instructions are under 32-bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 i 0 op1 S Rn 0 imm3 Rd imm8
Decode fields Instruction Details
op1 S Rn Rd
0000 0 AND, ANDS (immediate)AND
0000 1 != 1111 AND, ANDS (immediate)ANDS
0000 1 1111 TST (immediate)
0001 BIC, BICS (immediate)
0010 0 != 1111 ORR, ORRS (immediate)ORR
0010 0 1111 MOV, MOVS (immediate)MOV
0010 1 != 1111 ORR, ORRS (immediate)ORRS
0010 1 1111 MOV, MOVS (immediate)MOVS
0011 0 != 1111 ORN, ORNS (immediate)not flag setting
0011 0 1111 MVN, MVNS (immediate)MVN
0011 1 != 1111 ORN, ORNS (immediate)flag setting
0011 1 1111 MVN, MVNS (immediate)MVNS
0100 0 EOR, EORS (immediate)EOR
0100 1 != 1111 EOR, EORS (immediate)EORS
0100 1 1111 TEQ (immediate)
0101 UNALLOCATED
011x UNALLOCATED
1000 0 != 1101 ADD, ADDS (immediate)ADD
1000 0 1101 ADD, ADDS (SP plus immediate)ADD
1000 1 != 1101 != 1111 ADD, ADDS (immediate)ADDS
1000 1 1101 != 1111 ADD, ADDS (SP plus immediate)ADDS
1000 1 1111 CMN (immediate)
1001 UNALLOCATED
1010 ADC, ADCS (immediate)
1011 SBC, SBCS (immediate)
1100 UNALLOCATED
1101 0 != 1101 SUB, SUBS (immediate)SUB
1101 0 1101 SUB, SUBS (SP minus immediate)SUB
1101 1 != 1101 != 1111 SUB, SUBS (immediate)SUBS
1101 1 1101 != 1111 SUB, SUBS (SP minus immediate)SUBS
1101 1 1111 CMP (immediate)
1110 RSB, RSBS (immediate)
1111 UNALLOCATED

Data-processing (plain binary immediate)

These instructions are under 32-bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
11110 1 op0 op1 0 0
Decode fields Instruction details
op0 op1
0 0x Data-processing (simple immediate)
0 10 Move Wide (16-bit immediate)
0 11 UNALLOCATED
1 Saturate, Bitfield

Data-processing (simple immediate)

These instructions are under Data-processing (plain binary immediate).

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 i 1 0 o1 0 o2 0 Rn 0 imm3 Rd imm8
Decode fields Instruction Details
o1 o2 Rn
0 0 != 11x1 ADD, ADDS (immediate)
0 0 1101 ADD, ADDS (SP plus immediate)
0 0 1111 ADRT3
0 1 UNALLOCATED
1 0 UNALLOCATED
1 1 != 11x1 SUB, SUBS (immediate)
1 1 1101 SUB, SUBS (SP minus immediate)
1 1 1111 ADRT2

Move Wide (16-bit immediate)

These instructions are under Data-processing (plain binary immediate).

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 i 1 0 o1 1 0 0 imm4 0 imm3 Rd imm8
Decode fields Instruction Details
o1
0 MOV, MOVS (immediate)
1 MOVT

Saturate, Bitfield

These instructions are under Data-processing (plain binary immediate).

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 (0) 1 1 op1 0 Rn 0 imm3 Rd imm2 (0) widthm1
Decode fields Instruction Details
op1 Rn imm3:imm2
000 SSATlogical shift left
001 != 00000 SSATarithmetic shift right
001 00000 SSAT16
010 SBFX
011 != 1111 BFI
011 1111 BFC
100 USATlogical shift left
101 != 00000 USATarithmetic shift right
101 00000 USAT16
110 UBFX
111 UNALLOCATED

Advanced SIMD element or structure load/store

These instructions are under 32-bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
11111001 op0 0 op1

Advanced SIMD load/store multiple structures

These instructions are under Advanced SIMD element or structure load/store.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 1 0 D L 0 Rn Vd itype size align Rm

Advanced SIMD load single structure to all lanes

These instructions are under Advanced SIMD element or structure load/store.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 1 1 D L 0 Rn Vd 1 1 N size T a Rm

Advanced SIMD load/store single structure to one lane

These instructions are under Advanced SIMD element or structure load/store.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 1 1 D L 0 Rn Vd != 11 N index_align Rm
size

The following constraints also apply to this encoding: size != 11 && size != 11


Load/store single

These instructions are under 32-bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1111100 op0 op1 op2 op3

The following constraints also apply to this encoding: op0<1>:op1 != 10

Decode fields Instruction details
op0 op1 op2 op3
00 != 1111 000000 Load/store, unsigned (register offset)
00 != 1111 000001 UNALLOCATED
00 != 1111 00001x UNALLOCATED
00 != 1111 0001xx UNALLOCATED
00 != 1111 001xxx UNALLOCATED
00 != 1111 01xxxx UNALLOCATED
00 != 1111 10x0xx UNALLOCATED
00 != 1111 10x1xx Load/store, unsigned (immediate, post-indexed)
00 != 1111 1100xx Load/store, unsigned (negative immediate)
00 != 1111 1110xx Load/store, unsigned (unprivileged)
00 != 1111 11x1xx Load/store, unsigned (immediate, pre-indexed)
01 != 1111 Load/store, unsigned (positive immediate)
0x 1111 Load, unsigned (literal)
10 1 != 1111 000000 Load/store, signed (register offset)
10 1 != 1111 000001 UNALLOCATED
10 1 != 1111 00001x UNALLOCATED
10 1 != 1111 0001xx UNALLOCATED
10 1 != 1111 001xxx UNALLOCATED
10 1 != 1111 01xxxx UNALLOCATED
10 1 != 1111 10x0xx UNALLOCATED
10 1 != 1111 10x1xx Load/store, signed (immediate, post-indexed)
10 1 != 1111 1100xx Load/store, signed (negative immediate)
10 1 != 1111 1110xx Load/store, signed (unprivileged)
10 1 != 1111 11x1xx Load/store, signed (immediate, pre-indexed)
11 1 != 1111 Load/store, signed (positive immediate)
1x 1 1111 Load, signed (literal)

Load/store, unsigned (register offset)

These instructions are under Load/store single.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 0 0 size L != 1111 Rt 0 0 0 0 0 0 imm2 Rm
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
size L Rt
00 0 STRB (register)
00 1 != 1111 LDRB (register)
00 1 1111 PLD, PLDW (register)preload read
01 0 STRH (register)
01 1 != 1111 LDRH (register)
01 1 1111 PLD, PLDW (register)preload write
10 0 STR (register)
10 1 LDR (register)
11 UNALLOCATED

Load/store, unsigned (immediate, post-indexed)

These instructions are under Load/store single.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 0 0 size L != 1111 Rt 1 0 U 1 imm8
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
size L
00 0 STRB (immediate)
00 1 LDRB (immediate)
01 0 STRH (immediate)
01 1 LDRH (immediate)
10 0 STR (immediate)
10 1 LDR (immediate)
11 UNALLOCATED

Load/store, unsigned (negative immediate)

These instructions are under Load/store single.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 0 0 size L != 1111 Rt 1 1 0 0 imm8
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
size L Rt
00 0 STRB (immediate)
00 1 != 1111 LDRB (immediate)
00 1 1111 PLD, PLDW (immediate)preload read
01 0 STRH (immediate)
01 1 != 1111 LDRH (immediate)
01 1 1111 PLD, PLDW (immediate)preload write
10 0 STR (immediate)
10 1 LDR (immediate)
11 UNALLOCATED

Load/store, unsigned (unprivileged)

These instructions are under Load/store single.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 0 0 size L != 1111 Rt 1 1 1 0 imm8
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
size L
00 0 STRBT
00 1 LDRBT
01 0 STRHT
01 1 LDRHT
10 0 STRT
10 1 LDRT
11 UNALLOCATED

Load/store, unsigned (immediate, pre-indexed)

These instructions are under Load/store single.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 0 0 size L != 1111 Rt 1 1 U 1 imm8
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
size L
00 0 STRB (immediate)
00 1 LDRB (immediate)
01 0 STRH (immediate)
01 1 LDRH (immediate)
10 0 STR (immediate)
10 1 LDR (immediate)
11 UNALLOCATED

Load/store, unsigned (positive immediate)

These instructions are under Load/store single.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 0 1 size L != 1111 Rt imm12
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
size L Rt
00 0 STRB (immediate)
00 1 != 1111 LDRB (immediate)
00 1 1111 PLD, PLDW (immediate)preload read
01 0 STRH (immediate)
01 1 != 1111 LDRH (immediate)
01 1 1111 PLD, PLDW (immediate)preload write
10 0 STR (immediate)
10 1 LDR (immediate)

Load, unsigned (literal)

These instructions are under Load/store single.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 0 U size L 1 1 1 1 Rt imm12
Decode fields Instruction Details
size L Rt
0x 1 1111 PLD (literal)
00 1 != 1111 LDRB (literal)
01 1 != 1111 LDRH (literal)
10 1 LDR (literal)
11 UNALLOCATED

Load/store, signed (register offset)

These instructions are under Load/store single.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 1 0 size 1 != 1111 Rt 0 0 0 0 0 0 imm2 Rm
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
size Rt
00 != 1111 LDRSB (register)
00 1111 PLI (register)
01 != 1111 LDRSH (register)
01 1111 Reserved hint, behaves as NOP
1x UNALLOCATED

Load/store, signed (immediate, post-indexed)

These instructions are under Load/store single.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 1 0 size 1 != 1111 Rt 1 0 U 1 imm8
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
size
00 LDRSB (immediate)
01 LDRSH (immediate)
1x UNALLOCATED

Load/store, signed (negative immediate)

These instructions are under Load/store single.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 1 0 size 1 != 1111 Rt 1 1 0 0 imm8
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
size Rt
00 != 1111 LDRSB (immediate)
00 1111 PLI (immediate, literal)
01 != 1111 LDRSH (immediate)
01 1111 Reserved hint, behaves as NOP
1x UNALLOCATED

Load/store, signed (unprivileged)

These instructions are under Load/store single.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 1 0 size 1 != 1111 Rt 1 1 1 0 imm8
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
size
00 LDRSBT
01 LDRSHT
1x UNALLOCATED

Load/store, signed (immediate, pre-indexed)

These instructions are under Load/store single.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 1 0 size 1 != 1111 Rt 1 1 U 1 imm8
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
size
00 LDRSB (immediate)
01 LDRSH (immediate)
1x UNALLOCATED

Load/store, signed (positive immediate)

These instructions are under Load/store single.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 1 1 size 1 != 1111 Rt imm12
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
size Rt
00 != 1111 LDRSB (immediate)
00 1111 PLI (immediate, literal)
01 != 1111 LDRSH (immediate)
01 1111 Reserved hint, behaves as NOP

Load, signed (literal)

These instructions are under Load/store single.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 1 U size 1 1 1 1 1 Rt imm12
Decode fields Instruction Details
size Rt
00 != 1111 LDRSB (literal)
00 1111 PLI (immediate, literal)
01 != 1111 LDRSH (literal)
01 1111 Reserved hint, behaves as NOP
1x UNALLOCATED

Data-processing (register)

These instructions are under 32-bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
11111010 op0 op1 op2
Decode fields Instruction details
op0 op1 op2
0 1111 0000 MOV, MOVS (register-shifted register)T2, Flag setting
0 1111 0001 UNALLOCATED
0 1111 001x UNALLOCATED
0 1111 01xx UNALLOCATED
0 1111 1xxx Register extends
1 1111 0xxx Parallel add-subtract
1 1111 10xx Data-processing (two source registers)
1 1111 11xx UNALLOCATED
!= 1111 UNALLOCATED

Register extends

These instructions are under Data-processing (register).

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 1 0 0 op1 U Rn 1 1 1 1 Rd 1 (0) rotate Rm
Decode fields Instruction Details
op1 U Rn
00 0 != 1111 SXTAH
00 0 1111 SXTH
00 1 != 1111 UXTAH
00 1 1111 UXTH
01 0 != 1111 SXTAB16
01 0 1111 SXTB16
01 1 != 1111 UXTAB16
01 1 1111 UXTB16
10 0 != 1111 SXTAB
10 0 1111 SXTB
10 1 != 1111 UXTAB
10 1 1111 UXTB
11 UNALLOCATED

Parallel add-subtract

These instructions are under Data-processing (register).

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 1 0 1 op1 Rn 1 1 1 1 Rd 0 U H S Rm
Decode fields Instruction Details
op1 U H S
000 0 0 0 SADD8
000 0 0 1 QADD8
000 0 1 0 SHADD8
000 0 1 1 UNALLOCATED
000 1 0 0 UADD8
000 1 0 1 UQADD8
000 1 1 0 UHADD8
000 1 1 1 UNALLOCATED
001 0 0 0 SADD16
001 0 0 1 QADD16
001 0 1 0 SHADD16
001 0 1 1 UNALLOCATED
001 1 0 0 UADD16
001 1 0 1 UQADD16
001 1 1 0 UHADD16
001 1 1 1 UNALLOCATED
010 0 0 0 SASX
010 0 0 1 QASX
010 0 1 0 SHASX
010 0 1 1 UNALLOCATED
010 1 0 0 UASX
010 1 0 1 UQASX
010 1 1 0 UHASX
010 1 1 1 UNALLOCATED
100 0 0 0 SSUB8
100 0 0 1 QSUB8
100 0 1 0 SHSUB8
100 0 1 1 UNALLOCATED
100 1 0 0 USUB8
100 1 0 1 UQSUB8
100 1 1 0 UHSUB8
100 1 1 1 UNALLOCATED
101 0 0 0 SSUB16
101 0 0 1 QSUB16
101 0 1 0 SHSUB16
101 0 1 1 UNALLOCATED
101 1 0 0 USUB16
101 1 0 1 UQSUB16
101 1 1 0 UHSUB16
101 1 1 1 UNALLOCATED
110 0 0 0 SSAX
110 0 0 1 QSAX
110 0 1 0 SHSAX
110 0 1 1 UNALLOCATED
110 1 0 0 USAX
110 1 0 1 UQSAX
110 1 1 0 UHSAX
110 1 1 1 UNALLOCATED
111 UNALLOCATED

Data-processing (two source registers)

These instructions are under Data-processing (register).

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 1 0 1 op1 Rn 1 1 1 1 Rd 1 0 op2 Rm
Decode fields Instruction Details
op1 op2
000 00 QADD
000 01 QDADD
000 10 QSUB
000 11 QDSUB
001 00 REV
001 01 REV16
001 10 RBIT
001 11 REVSH
010 00 SEL
010 01 UNALLOCATED
010 1x UNALLOCATED
011 00 CLZ
011 01 UNALLOCATED
011 1x UNALLOCATED
100 00 CRC32CRC32B
100 01 CRC32CRC32H
100 10 CRC32CRC32W
100 11 CONSTRAINED UNPREDICTABLE
101 00 CRC32CCRC32CB
101 01 CRC32CCRC32CH
101 10 CRC32CCRC32CW
101 11 CONSTRAINED UNPREDICTABLE
11x UNALLOCATED

The behavior of the CONSTRAINED UNPREDICTABLE encodings in this table is described in CONSTRAINED UNPREDICTABLE behavior for A32 and T32 instruction encodings


Multiply, multiply accumulate, and absolute difference

These instructions are under 32-bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
111110110 op0
Decode fields Instruction details
op0
00 Multiply and absolute difference
01 UNALLOCATED
1x UNALLOCATED

Multiply and absolute difference

These instructions are under Multiply, multiply accumulate, and absolute difference.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 1 1 0 op1 Rn Ra Rd 0 0 op2 Rm
Decode fields Instruction Details
op1 Ra op2
000 != 1111 00 MLA, MLAS
000 01 MLS
000 1x UNALLOCATED
000 1111 00 MUL, MULS
001 != 1111 00 SMLABB, SMLABT, SMLATB, SMLATTSMLABB
001 != 1111 01 SMLABB, SMLABT, SMLATB, SMLATTSMLABT
001 != 1111 10 SMLABB, SMLABT, SMLATB, SMLATTSMLATB
001 != 1111 11 SMLABB, SMLABT, SMLATB, SMLATTSMLATT
001 1111 00 SMULBB, SMULBT, SMULTB, SMULTTSMULBB
001 1111 01 SMULBB, SMULBT, SMULTB, SMULTTSMULBT
001 1111 10 SMULBB, SMULBT, SMULTB, SMULTTSMULTB
001 1111 11 SMULBB, SMULBT, SMULTB, SMULTTSMULTT
010 != 1111 00 SMLAD, SMLADXSMLAD
010 != 1111 01 SMLAD, SMLADXSMLADX
010 1x UNALLOCATED
010 1111 00 SMUAD, SMUADXSMUAD
010 1111 01 SMUAD, SMUADXSMUADX
011 != 1111 00 SMLAWB, SMLAWTSMLAWB
011 != 1111 01 SMLAWB, SMLAWTSMLAWT
011 1x UNALLOCATED
011 1111 00 SMULWB, SMULWTSMULWB
011 1111 01 SMULWB, SMULWTSMULWT
100 != 1111 00 SMLSD, SMLSDXSMLSD
100 != 1111 01 SMLSD, SMLSDXSMLSDX
100 1x UNALLOCATED
100 1111 00 SMUSD, SMUSDXSMUSD
100 1111 01 SMUSD, SMUSDXSMUSDX
101 != 1111 00 SMMLA, SMMLARSMMLA
101 != 1111 01 SMMLA, SMMLARSMMLAR
101 1x UNALLOCATED
101 1111 00 SMMUL, SMMULRSMMUL
101 1111 01 SMMUL, SMMULRSMMULR
110 00 SMMLS, SMMLSRSMMLS
110 01 SMMLS, SMMLSRSMMLSR
110 1x UNALLOCATED
111 != 1111 00 USADA8
111 01 UNALLOCATED
111 1x UNALLOCATED
111 1111 00 USAD8

Long multiply and divide

These instructions are under 32-bit.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 1 1 1 op1 Rn RdLo RdHi op2 Rm
Decode fields Instruction Details
op1 op2
000 != 0000 UNALLOCATED
000 0000 SMULL, SMULLS
001 != 1111 UNALLOCATED
001 1111 SDIV
010 != 0000 UNALLOCATED
010 0000 UMULL, UMULLS
011 != 1111 UNALLOCATED
011 1111 UDIV
100 0000 SMLAL, SMLALS
100 0001 UNALLOCATED
100 001x UNALLOCATED
100 01xx UNALLOCATED
100 1000 SMLALBB, SMLALBT, SMLALTB, SMLALTTSMLALBB
100 1001 SMLALBB, SMLALBT, SMLALTB, SMLALTTSMLALBT
100 1010 SMLALBB, SMLALBT, SMLALTB, SMLALTTSMLALTB
100 1011 SMLALBB, SMLALBT, SMLALTB, SMLALTTSMLALTT
100 1100 SMLALD, SMLALDXSMLALD
100 1101 SMLALD, SMLALDXSMLALDX
100 111x UNALLOCATED
101 0xxx UNALLOCATED
101 10xx UNALLOCATED
101 1100 SMLSLD, SMLSLDXSMLSLD
101 1101 SMLSLD, SMLSLDXSMLSLDX
101 111x UNALLOCATED
110 0000 UMLAL, UMLALS
110 0001 UNALLOCATED
110 001x UNALLOCATED
110 010x UNALLOCATED
110 0110 UMAAL
110 0111 UNALLOCATED
110 1xxx UNALLOCATED
111 UNALLOCATED