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BX

Branch and Exchange causes a branch to an address and instruction set specified by a register.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 111100010010(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)0001Rm
cond

A1

BX{<c>}{<q>} <Rm>

m = UInt(Rm);

T1

1514131211109876543210
010001110Rm(0)(0)(0)

T1

BX{<c>}{<q>} <Rm>

m = UInt(Rm);
if InITBlock() && !LastInITBlock() then UNPREDICTABLE;

For more information about the constrained unpredictable behavior, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rm>

For encoding A1: is the general-purpose register holding the address to be branched to, encoded in the "Rm" field. The PC can be used.

For encoding T1: is the general-purpose register holding the address to be branched to, encoded in the "Rm" field. The PC can be used.

If <Rm> is the PC at a non word-aligned address, it results in unpredictable behavior because the address passed to the BXWritePC() pseudocode function has bits<1:0> = '10'.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    BXWritePC(R[m], BranchType_INDIR);
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